Geert Uytterhoeven c86a4b6219 ARM: dts: r8a73a4: Add L2 cache-controller nodes ... Add device nodes for the L2 caches, and link the CPU node to its L2 cache node. The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as 64 KiB x 16 ways), and located in PM domain A3SM. The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as 64 KiB x 8 ways), and located in PM domain A3KM. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>		2016-02-19 14:52:21 +09:00
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bootp
compressed	ARM: add UEFI stub support	2015-12-14 10:38:21 +01:00
dts	ARM: dts: r8a73a4: Add L2 cache-controller nodes	2016-02-19 14:52:21 +09:00
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