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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a88f666707
DMA_CTRL_ACK's description applies to its clear state, not to its set state. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
635 lines
20 KiB
C
635 lines
20 KiB
C
/*
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* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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#ifndef DMAENGINE_H
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#define DMAENGINE_H
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#include <linux/device.h>
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#include <linux/uio.h>
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#include <linux/dma-mapping.h>
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/**
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* typedef dma_cookie_t - an opaque DMA cookie
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*
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* if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
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*/
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typedef s32 dma_cookie_t;
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#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
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/**
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* enum dma_status - DMA transaction status
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* @DMA_SUCCESS: transaction completed successfully
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* @DMA_IN_PROGRESS: transaction not yet processed
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* @DMA_ERROR: transaction failed
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*/
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enum dma_status {
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DMA_SUCCESS,
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DMA_IN_PROGRESS,
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DMA_ERROR,
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};
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/**
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* enum dma_transaction_type - DMA transaction types/indexes
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*
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* Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
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* automatically set as dma devices are registered.
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*/
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enum dma_transaction_type {
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DMA_MEMCPY,
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DMA_XOR,
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DMA_PQ,
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DMA_XOR_VAL,
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DMA_PQ_VAL,
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DMA_MEMSET,
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DMA_INTERRUPT,
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DMA_PRIVATE,
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DMA_ASYNC_TX,
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DMA_SLAVE,
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};
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/* last transaction type for creation of the capabilities mask */
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#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
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/**
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* enum dma_ctrl_flags - DMA flags to augment operation preparation,
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* control completion, and communicate status.
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* @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
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* this transaction
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* @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
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* acknowledges receipt, i.e. has has a chance to establish any dependency
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* chains
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* @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
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* @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
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* @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
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* (if not set, do the source dma-unmapping as page)
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* @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
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* (if not set, do the destination dma-unmapping as page)
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* @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
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* @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
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* @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
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* sources that were the result of a previous operation, in the case of a PQ
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* operation it continues the calculation with new sources
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* @DMA_PREP_FENCE - tell the driver that subsequent operations depend
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* on the result of this operation
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*/
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enum dma_ctrl_flags {
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DMA_PREP_INTERRUPT = (1 << 0),
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DMA_CTRL_ACK = (1 << 1),
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DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
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DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
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DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
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DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
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DMA_PREP_PQ_DISABLE_P = (1 << 6),
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DMA_PREP_PQ_DISABLE_Q = (1 << 7),
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DMA_PREP_CONTINUE = (1 << 8),
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DMA_PREP_FENCE = (1 << 9),
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};
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/**
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* enum sum_check_bits - bit position of pq_check_flags
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*/
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enum sum_check_bits {
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SUM_CHECK_P = 0,
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SUM_CHECK_Q = 1,
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};
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/**
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* enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
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* @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
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* @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
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*/
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enum sum_check_flags {
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SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
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SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
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};
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/**
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* dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
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* See linux/cpumask.h
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*/
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typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
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/**
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* struct dma_chan_percpu - the per-CPU part of struct dma_chan
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* @memcpy_count: transaction counter
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* @bytes_transferred: byte counter
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*/
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struct dma_chan_percpu {
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/* stats */
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unsigned long memcpy_count;
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unsigned long bytes_transferred;
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};
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/**
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* struct dma_chan - devices supply DMA channels, clients use them
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* @device: ptr to the dma device who supplies this channel, always !%NULL
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* @cookie: last cookie value returned to client
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* @chan_id: channel ID for sysfs
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* @dev: class device for sysfs
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* @device_node: used to add this to the device chan list
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* @local: per-cpu pointer to a struct dma_chan_percpu
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* @client-count: how many clients are using this channel
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* @table_count: number of appearances in the mem-to-mem allocation table
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* @private: private data for certain client-channel associations
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*/
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struct dma_chan {
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struct dma_device *device;
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dma_cookie_t cookie;
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/* sysfs */
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int chan_id;
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struct dma_chan_dev *dev;
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struct list_head device_node;
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struct dma_chan_percpu *local;
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int client_count;
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int table_count;
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void *private;
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};
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/**
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* struct dma_chan_dev - relate sysfs device node to backing channel device
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* @chan - driver channel device
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* @device - sysfs device
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* @dev_id - parent dma_device dev_id
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* @idr_ref - reference count to gate release of dma_device dev_id
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*/
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struct dma_chan_dev {
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struct dma_chan *chan;
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struct device device;
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int dev_id;
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atomic_t *idr_ref;
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};
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static inline const char *dma_chan_name(struct dma_chan *chan)
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{
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return dev_name(&chan->dev->device);
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}
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void dma_chan_cleanup(struct kref *kref);
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/**
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* typedef dma_filter_fn - callback filter for dma_request_channel
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* @chan: channel to be reviewed
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* @filter_param: opaque parameter passed through dma_request_channel
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*
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* When this optional parameter is specified in a call to dma_request_channel a
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* suitable channel is passed to this routine for further dispositioning before
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* being returned. Where 'suitable' indicates a non-busy channel that
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* satisfies the given capability mask. It returns 'true' to indicate that the
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* channel is suitable.
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*/
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typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
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typedef void (*dma_async_tx_callback)(void *dma_async_param);
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/**
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* struct dma_async_tx_descriptor - async transaction descriptor
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* ---dma generic offload fields---
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* @cookie: tracking cookie for this transaction, set to -EBUSY if
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* this tx is sitting on a dependency list
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* @flags: flags to augment operation preparation, control completion, and
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* communicate status
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* @phys: physical address of the descriptor
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* @chan: target channel for this operation
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* @tx_submit: set the prepared descriptor(s) to be executed by the engine
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* @callback: routine to call after this operation is complete
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* @callback_param: general parameter to pass to the callback routine
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* ---async_tx api specific fields---
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* @next: at completion submit this descriptor
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* @parent: pointer to the next level up in the dependency chain
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* @lock: protect the parent and next pointers
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*/
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struct dma_async_tx_descriptor {
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dma_cookie_t cookie;
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enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
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dma_addr_t phys;
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struct dma_chan *chan;
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dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
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dma_async_tx_callback callback;
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void *callback_param;
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struct dma_async_tx_descriptor *next;
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struct dma_async_tx_descriptor *parent;
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spinlock_t lock;
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};
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/**
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* struct dma_device - info on the entity supplying DMA services
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* @chancnt: how many DMA channels are supported
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* @privatecnt: how many DMA channels are requested by dma_request_channel
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* @channels: the list of struct dma_chan
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* @global_node: list_head for global dma_device_list
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* @cap_mask: one or more dma_capability flags
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* @max_xor: maximum number of xor sources, 0 if no capability
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* @max_pq: maximum number of PQ sources and PQ-continue capability
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* @copy_align: alignment shift for memcpy operations
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* @xor_align: alignment shift for xor operations
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* @pq_align: alignment shift for pq operations
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* @fill_align: alignment shift for memset operations
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* @dev_id: unique device ID
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* @dev: struct device reference for dma mapping api
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* @device_alloc_chan_resources: allocate resources and return the
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* number of allocated descriptors
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* @device_free_chan_resources: release DMA channel's resources
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* @device_prep_dma_memcpy: prepares a memcpy operation
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* @device_prep_dma_xor: prepares a xor operation
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* @device_prep_dma_xor_val: prepares a xor validation operation
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* @device_prep_dma_pq: prepares a pq operation
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* @device_prep_dma_pq_val: prepares a pqzero_sum operation
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* @device_prep_dma_memset: prepares a memset operation
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* @device_prep_dma_interrupt: prepares an end of chain interrupt operation
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* @device_prep_slave_sg: prepares a slave dma operation
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* @device_terminate_all: terminate all pending operations
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* @device_is_tx_complete: poll for transaction completion
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* @device_issue_pending: push pending transactions to hardware
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*/
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struct dma_device {
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unsigned int chancnt;
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unsigned int privatecnt;
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struct list_head channels;
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struct list_head global_node;
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dma_cap_mask_t cap_mask;
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unsigned short max_xor;
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unsigned short max_pq;
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u8 copy_align;
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u8 xor_align;
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u8 pq_align;
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u8 fill_align;
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#define DMA_HAS_PQ_CONTINUE (1 << 15)
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int dev_id;
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struct device *dev;
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int (*device_alloc_chan_resources)(struct dma_chan *chan);
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void (*device_free_chan_resources)(struct dma_chan *chan);
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struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
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struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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size_t len, unsigned long flags);
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struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
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struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
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unsigned int src_cnt, size_t len, unsigned long flags);
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struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
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struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
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size_t len, enum sum_check_flags *result, unsigned long flags);
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struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
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struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
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unsigned int src_cnt, const unsigned char *scf,
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size_t len, unsigned long flags);
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struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
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struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
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unsigned int src_cnt, const unsigned char *scf, size_t len,
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enum sum_check_flags *pqres, unsigned long flags);
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struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
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struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
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unsigned long flags);
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struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
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struct dma_chan *chan, unsigned long flags);
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struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
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struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_data_direction direction,
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unsigned long flags);
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void (*device_terminate_all)(struct dma_chan *chan);
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enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
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dma_cookie_t cookie, dma_cookie_t *last,
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dma_cookie_t *used);
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void (*device_issue_pending)(struct dma_chan *chan);
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};
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static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
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{
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size_t mask;
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if (!align)
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return true;
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mask = (1 << align) - 1;
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if (mask & (off1 | off2 | len))
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return false;
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return true;
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}
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static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
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size_t off2, size_t len)
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{
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return dmaengine_check_align(dev->copy_align, off1, off2, len);
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}
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static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
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size_t off2, size_t len)
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{
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return dmaengine_check_align(dev->xor_align, off1, off2, len);
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}
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static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
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size_t off2, size_t len)
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{
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return dmaengine_check_align(dev->pq_align, off1, off2, len);
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}
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static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
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size_t off2, size_t len)
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{
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return dmaengine_check_align(dev->fill_align, off1, off2, len);
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}
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static inline void
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dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
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{
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dma->max_pq = maxpq;
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if (has_pq_continue)
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dma->max_pq |= DMA_HAS_PQ_CONTINUE;
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}
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static inline bool dmaf_continue(enum dma_ctrl_flags flags)
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{
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return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
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}
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static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
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{
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enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
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return (flags & mask) == mask;
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}
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static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
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{
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return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
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}
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static unsigned short dma_dev_to_maxpq(struct dma_device *dma)
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{
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return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
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}
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/* dma_maxpq - reduce maxpq in the face of continued operations
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* @dma - dma device with PQ capability
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* @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
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*
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* When an engine does not support native continuation we need 3 extra
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* source slots to reuse P and Q with the following coefficients:
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* 1/ {00} * P : remove P from Q', but use it as a source for P'
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* 2/ {01} * Q : use Q to continue Q' calculation
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* 3/ {00} * Q : subtract Q from P' to cancel (2)
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*
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* In the case where P is disabled we only need 1 extra source:
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* 1/ {01} * Q : use Q to continue Q' calculation
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*/
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static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
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{
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if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
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return dma_dev_to_maxpq(dma);
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else if (dmaf_p_disabled_continue(flags))
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return dma_dev_to_maxpq(dma) - 1;
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else if (dmaf_continue(flags))
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return dma_dev_to_maxpq(dma) - 3;
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BUG();
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}
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/* --- public DMA engine API --- */
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#ifdef CONFIG_DMA_ENGINE
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void dmaengine_get(void);
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void dmaengine_put(void);
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#else
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static inline void dmaengine_get(void)
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{
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}
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static inline void dmaengine_put(void)
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{
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}
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#endif
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#ifdef CONFIG_NET_DMA
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#define net_dmaengine_get() dmaengine_get()
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#define net_dmaengine_put() dmaengine_put()
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#else
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static inline void net_dmaengine_get(void)
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{
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}
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static inline void net_dmaengine_put(void)
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{
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}
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#endif
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#ifdef CONFIG_ASYNC_TX_DMA
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#define async_dmaengine_get() dmaengine_get()
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#define async_dmaengine_put() dmaengine_put()
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#ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
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#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
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#else
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#define async_dma_find_channel(type) dma_find_channel(type)
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#endif /* CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH */
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#else
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static inline void async_dmaengine_get(void)
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{
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}
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static inline void async_dmaengine_put(void)
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{
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}
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static inline struct dma_chan *
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async_dma_find_channel(enum dma_transaction_type type)
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{
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return NULL;
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}
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#endif /* CONFIG_ASYNC_TX_DMA */
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dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
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void *dest, void *src, size_t len);
|
|
dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
|
|
struct page *page, unsigned int offset, void *kdata, size_t len);
|
|
dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
|
|
struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
|
|
unsigned int src_off, size_t len);
|
|
void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
|
|
struct dma_chan *chan);
|
|
|
|
static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
|
|
{
|
|
tx->flags |= DMA_CTRL_ACK;
|
|
}
|
|
|
|
static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
|
|
{
|
|
tx->flags &= ~DMA_CTRL_ACK;
|
|
}
|
|
|
|
static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
|
|
{
|
|
return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
|
|
}
|
|
|
|
#define first_dma_cap(mask) __first_dma_cap(&(mask))
|
|
static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
|
|
{
|
|
return min_t(int, DMA_TX_TYPE_END,
|
|
find_first_bit(srcp->bits, DMA_TX_TYPE_END));
|
|
}
|
|
|
|
#define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
|
|
static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
|
|
{
|
|
return min_t(int, DMA_TX_TYPE_END,
|
|
find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
|
|
}
|
|
|
|
#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
|
|
static inline void
|
|
__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
|
|
{
|
|
set_bit(tx_type, dstp->bits);
|
|
}
|
|
|
|
#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
|
|
static inline void
|
|
__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
|
|
{
|
|
clear_bit(tx_type, dstp->bits);
|
|
}
|
|
|
|
#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
|
|
static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
|
|
{
|
|
bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
|
|
}
|
|
|
|
#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
|
|
static inline int
|
|
__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
|
|
{
|
|
return test_bit(tx_type, srcp->bits);
|
|
}
|
|
|
|
#define for_each_dma_cap_mask(cap, mask) \
|
|
for ((cap) = first_dma_cap(mask); \
|
|
(cap) < DMA_TX_TYPE_END; \
|
|
(cap) = next_dma_cap((cap), (mask)))
|
|
|
|
/**
|
|
* dma_async_issue_pending - flush pending transactions to HW
|
|
* @chan: target DMA channel
|
|
*
|
|
* This allows drivers to push copies to HW in batches,
|
|
* reducing MMIO writes where possible.
|
|
*/
|
|
static inline void dma_async_issue_pending(struct dma_chan *chan)
|
|
{
|
|
chan->device->device_issue_pending(chan);
|
|
}
|
|
|
|
#define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
|
|
|
|
/**
|
|
* dma_async_is_tx_complete - poll for transaction completion
|
|
* @chan: DMA channel
|
|
* @cookie: transaction identifier to check status of
|
|
* @last: returns last completed cookie, can be NULL
|
|
* @used: returns last issued cookie, can be NULL
|
|
*
|
|
* If @last and @used are passed in, upon return they reflect the driver
|
|
* internal state and can be used with dma_async_is_complete() to check
|
|
* the status of multiple cookies without re-checking hardware state.
|
|
*/
|
|
static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
|
|
dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
|
|
{
|
|
return chan->device->device_is_tx_complete(chan, cookie, last, used);
|
|
}
|
|
|
|
#define dma_async_memcpy_complete(chan, cookie, last, used)\
|
|
dma_async_is_tx_complete(chan, cookie, last, used)
|
|
|
|
/**
|
|
* dma_async_is_complete - test a cookie against chan state
|
|
* @cookie: transaction identifier to test status of
|
|
* @last_complete: last know completed transaction
|
|
* @last_used: last cookie value handed out
|
|
*
|
|
* dma_async_is_complete() is used in dma_async_memcpy_complete()
|
|
* the test logic is separated for lightweight testing of multiple cookies
|
|
*/
|
|
static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
|
|
dma_cookie_t last_complete, dma_cookie_t last_used)
|
|
{
|
|
if (last_complete <= last_used) {
|
|
if ((cookie <= last_complete) || (cookie > last_used))
|
|
return DMA_SUCCESS;
|
|
} else {
|
|
if ((cookie <= last_complete) && (cookie > last_used))
|
|
return DMA_SUCCESS;
|
|
}
|
|
return DMA_IN_PROGRESS;
|
|
}
|
|
|
|
enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
|
|
#ifdef CONFIG_DMA_ENGINE
|
|
enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
|
|
void dma_issue_pending_all(void);
|
|
#else
|
|
static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
|
|
{
|
|
return DMA_SUCCESS;
|
|
}
|
|
static inline void dma_issue_pending_all(void)
|
|
{
|
|
do { } while (0);
|
|
}
|
|
#endif
|
|
|
|
/* --- DMA device --- */
|
|
|
|
int dma_async_device_register(struct dma_device *device);
|
|
void dma_async_device_unregister(struct dma_device *device);
|
|
void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
|
|
struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
|
|
#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
|
|
struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
|
|
void dma_release_channel(struct dma_chan *chan);
|
|
|
|
/* --- Helper iov-locking functions --- */
|
|
|
|
struct dma_page_list {
|
|
char __user *base_address;
|
|
int nr_pages;
|
|
struct page **pages;
|
|
};
|
|
|
|
struct dma_pinned_list {
|
|
int nr_iovecs;
|
|
struct dma_page_list page_list[0];
|
|
};
|
|
|
|
struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
|
|
void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
|
|
|
|
dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
|
|
struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
|
|
dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
|
|
struct dma_pinned_list *pinned_list, struct page *page,
|
|
unsigned int offset, size_t len);
|
|
|
|
#endif /* DMAENGINE_H */
|