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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c7ed1ab3f7
This fixes up some of the I/D/F clock ambiguity in the sh-sci driver. The interface clock in most cases just wraps back to the peripheral clock, while the function clock wraps in to the MSTP bits. As the logic was somewhat inverted, this cleans that up, and also enables all CPUs with SCI MSTP bits to match function clocks through clkdev lookup. As a result, this gets rid of the clk string abuse on the sh side, and the clock string will be killed off once the ARM code has had a chance to sync up. This also enables MSTP gating on CPUs like 7786 which had never wired it up before. Impacted CPUs are primarily all SH-Mobiles, SH7785, and SH7786. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
246 lines
7.4 KiB
C
246 lines
7.4 KiB
C
/*
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* arch/sh/kernel/cpu/sh4a/clock-sh7723.c
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*
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* SH7723 clock framework support
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*
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* Copyright (C) 2009 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <asm/clock.h>
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#include <asm/hwblk.h>
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#include <cpu/sh7723.h>
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/* SH7723 registers */
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#define FRQCR 0xa4150000
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#define VCLKCR 0xa4150004
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#define SCLKACR 0xa4150008
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#define SCLKBCR 0xa415000c
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#define IRDACLKCR 0xa4150018
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#define PLLCR 0xa4150024
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#define DLLFRQ 0xa4150050
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/* Fixed 32 KHz root clock for RTC and Power Management purposes */
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static struct clk r_clk = {
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.name = "rclk",
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.id = -1,
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.rate = 32768,
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};
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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struct clk extal_clk = {
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.name = "extal",
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.id = -1,
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.rate = 33333333,
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};
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/* The dll multiplies the 32khz r_clk, may be used instead of extal */
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static unsigned long dll_recalc(struct clk *clk)
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{
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unsigned long mult;
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if (__raw_readl(PLLCR) & 0x1000)
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mult = __raw_readl(DLLFRQ);
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else
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mult = 0;
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return clk->parent->rate * mult;
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}
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static struct clk_ops dll_clk_ops = {
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.recalc = dll_recalc,
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};
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static struct clk dll_clk = {
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.name = "dll_clk",
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.id = -1,
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.ops = &dll_clk_ops,
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.parent = &r_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static unsigned long pll_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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unsigned long div = 1;
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if (__raw_readl(PLLCR) & 0x4000)
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mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
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else
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div = 2;
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return (clk->parent->rate * mult) / div;
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}
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static struct clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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static struct clk pll_clk = {
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.name = "pll_clk",
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.id = -1,
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.ops = &pll_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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};
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struct clk *main_clks[] = {
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&r_clk,
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&extal_clk,
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&dll_clk,
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&pll_clk,
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};
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static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
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static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = divisors,
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.nr_divisors = ARRAY_SIZE(divisors),
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.multipliers = multipliers,
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.nr_multipliers = ARRAY_SIZE(multipliers),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
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#define DIV4(_str, _reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
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[DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
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[DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
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};
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enum { DIV4_IRDA, DIV4_ENABLE_NR };
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struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
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[DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
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};
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enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
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struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
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[DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
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[DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
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};
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struct clk div6_clks[] = {
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SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
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};
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#define R_CLK (&r_clk)
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#define P_CLK (&div4_clks[DIV4_P])
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#define B_CLK (&div4_clks[DIV4_B])
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#define U_CLK (&div4_clks[DIV4_U])
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#define I_CLK (&div4_clks[DIV4_I])
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#define SH_CLK (&div4_clks[DIV4_SH])
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static struct clk mstp_clks[] = {
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/* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
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SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK("intc0", -1, I_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0),
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SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
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SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
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SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0),
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SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
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SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
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SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
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SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0),
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SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
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SH_HWBLK_CLK("sci_fck", 0, P_CLK, HWBLK_SCIF0, 0),
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SH_HWBLK_CLK("sci_fck", 1, P_CLK, HWBLK_SCIF1, 0),
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SH_HWBLK_CLK("sci_fck", 2, P_CLK, HWBLK_SCIF2, 0),
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SH_HWBLK_CLK("sci_fck", 3, B_CLK, HWBLK_SCIF3, 0),
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SH_HWBLK_CLK("sci_fck", 4, B_CLK, HWBLK_SCIF4, 0),
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SH_HWBLK_CLK("sci_fck", 5, B_CLK, HWBLK_SCIF5, 0),
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SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
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SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
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SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0),
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SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
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SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
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SH_HWBLK_CLK("atapi0", -1, SH_CLK, HWBLK_ATAPI, 0),
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SH_HWBLK_CLK("adc0", -1, P_CLK, HWBLK_ADC, 0),
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SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0),
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SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0),
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SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0),
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SH_HWBLK_CLK("icb0", -1, B_CLK, HWBLK_ICB, CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0),
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SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0),
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SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
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SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB, 0),
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SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
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SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
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SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU2H1, 0),
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SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
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SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
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SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
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SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU2H0, 0),
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SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
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SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
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};
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int __init arch_clk_init(void)
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{
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int k, ret = 0;
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/* autodetect extal or dll configuration */
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if (__raw_readl(PLLCR) & 0x1000)
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pll_clk.parent = &dll_clk;
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else
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pll_clk.parent = &extal_clk;
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
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ret = sh_clk_div4_enable_register(div4_enable_clks,
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DIV4_ENABLE_NR, &div4_table);
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if (!ret)
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ret = sh_clk_div4_reparent_register(div4_reparent_clks,
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DIV4_REPARENT_NR, &div4_table);
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if (!ret)
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ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
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if (!ret)
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ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks));
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return ret;
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}
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