mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a1606a9596
This commit breaks the userspace interface, and requires a new libdrm for nouveau to operate again. The multiple GEM_PUSHBUF ioctls that were present in 0.0.15 for compatibility purposes are now gone, and replaced with the new ioctl which allows for multiple push buffers to be submitted (necessary for hw index buffers in the nv50 3d driver) and relocations to be applied on any buffer. A number of other ioctls (CARD_INIT, GEM_PIN, GEM_UNPIN) that were needed for userspace modesetting have also been removed. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net>
200 lines
5.1 KiB
C
200 lines
5.1 KiB
C
/*
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* Copyright 2005 Stephane Marchesin.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __NOUVEAU_DRM_H__
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#define __NOUVEAU_DRM_H__
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#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
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struct drm_nouveau_channel_alloc {
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uint32_t fb_ctxdma_handle;
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uint32_t tt_ctxdma_handle;
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int channel;
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uint32_t pushbuf_domains;
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/* Notifier memory */
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uint32_t notifier_handle;
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/* DRM-enforced subchannel assignments */
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struct {
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uint32_t handle;
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uint32_t grclass;
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} subchan[8];
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uint32_t nr_subchan;
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};
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struct drm_nouveau_channel_free {
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int channel;
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};
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struct drm_nouveau_grobj_alloc {
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int channel;
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uint32_t handle;
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int class;
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};
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struct drm_nouveau_notifierobj_alloc {
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uint32_t channel;
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uint32_t handle;
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uint32_t size;
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uint32_t offset;
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};
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struct drm_nouveau_gpuobj_free {
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int channel;
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uint32_t handle;
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};
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/* FIXME : maybe unify {GET,SET}PARAMs */
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#define NOUVEAU_GETPARAM_PCI_VENDOR 3
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#define NOUVEAU_GETPARAM_PCI_DEVICE 4
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#define NOUVEAU_GETPARAM_BUS_TYPE 5
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#define NOUVEAU_GETPARAM_FB_PHYSICAL 6
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#define NOUVEAU_GETPARAM_AGP_PHYSICAL 7
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#define NOUVEAU_GETPARAM_FB_SIZE 8
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#define NOUVEAU_GETPARAM_AGP_SIZE 9
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#define NOUVEAU_GETPARAM_PCI_PHYSICAL 10
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#define NOUVEAU_GETPARAM_CHIPSET_ID 11
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#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
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#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
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struct drm_nouveau_getparam {
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uint64_t param;
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uint64_t value;
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};
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struct drm_nouveau_setparam {
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uint64_t param;
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uint64_t value;
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};
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#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
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#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
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#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
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#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
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struct drm_nouveau_gem_info {
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uint32_t handle;
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uint32_t domain;
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uint64_t size;
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uint64_t offset;
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uint64_t map_handle;
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uint32_t tile_mode;
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uint32_t tile_flags;
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};
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struct drm_nouveau_gem_new {
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struct drm_nouveau_gem_info info;
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uint32_t channel_hint;
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uint32_t align;
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};
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#define NOUVEAU_GEM_MAX_BUFFERS 1024
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struct drm_nouveau_gem_pushbuf_bo_presumed {
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uint32_t valid;
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uint32_t domain;
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uint64_t offset;
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};
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struct drm_nouveau_gem_pushbuf_bo {
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uint64_t user_priv;
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uint32_t handle;
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uint32_t read_domains;
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uint32_t write_domains;
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uint32_t valid_domains;
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struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
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};
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#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
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#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
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#define NOUVEAU_GEM_RELOC_OR (1 << 2)
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#define NOUVEAU_GEM_MAX_RELOCS 1024
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struct drm_nouveau_gem_pushbuf_reloc {
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uint32_t reloc_bo_index;
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uint32_t reloc_bo_offset;
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uint32_t bo_index;
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uint32_t flags;
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uint32_t data;
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uint32_t vor;
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uint32_t tor;
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};
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#define NOUVEAU_GEM_MAX_PUSH 512
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struct drm_nouveau_gem_pushbuf_push {
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uint32_t bo_index;
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uint32_t pad;
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uint64_t offset;
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uint64_t length;
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};
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struct drm_nouveau_gem_pushbuf {
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uint32_t channel;
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uint32_t nr_buffers;
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uint64_t buffers;
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uint32_t nr_relocs;
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uint32_t nr_push;
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uint64_t relocs;
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uint64_t push;
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uint32_t suffix0;
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uint32_t suffix1;
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uint64_t vram_available;
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uint64_t gart_available;
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};
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#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
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#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
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#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
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struct drm_nouveau_gem_cpu_prep {
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uint32_t handle;
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uint32_t flags;
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};
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struct drm_nouveau_gem_cpu_fini {
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uint32_t handle;
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};
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enum nouveau_bus_type {
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NV_AGP = 0,
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NV_PCI = 1,
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NV_PCIE = 2,
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};
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struct drm_nouveau_sarea {
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};
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#define DRM_NOUVEAU_GETPARAM 0x00
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#define DRM_NOUVEAU_SETPARAM 0x01
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#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
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#define DRM_NOUVEAU_CHANNEL_FREE 0x03
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#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
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#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
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#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
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#define DRM_NOUVEAU_GEM_NEW 0x40
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#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
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#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
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#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
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#define DRM_NOUVEAU_GEM_INFO 0x44
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#endif /* __NOUVEAU_DRM_H__ */
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