mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-20 00:27:24 +07:00
ef2b1d777d
The atlas7 clock controller driver registers a reset controller
for itself, which causes a link error when the subsystem is
disabled:
drivers/built-in.o: In function `atlas7_clk_init':
drivers/clk/sirf/clk-atlas7.c:1681: undefined reference to `reset_controller_register'
As the clk driver does not have a Kconfig symbol for itself
but it always built-in when the platform is enabled, we have
to ensure that the reset controller subsystem is also built-in
in this case.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Fixes: 301c5d2940 ("clk: sirf: add CSR atlas7 clk and reset support")
48 lines
972 B
Plaintext
48 lines
972 B
Plaintext
menuconfig ARCH_SIRF
|
|
bool "CSR SiRF"
|
|
depends on ARCH_MULTI_V7
|
|
select ARCH_HAS_RESET_CONTROLLER
|
|
select RESET_CONTROLLER
|
|
select ARCH_REQUIRE_GPIOLIB
|
|
select GENERIC_IRQ_CHIP
|
|
select NO_IOPORT_MAP
|
|
select REGMAP
|
|
select PINCTRL
|
|
select PINCTRL_SIRF
|
|
help
|
|
Support for CSR SiRFprimaII/Marco/Polo platforms
|
|
|
|
if ARCH_SIRF
|
|
|
|
comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features"
|
|
|
|
config ARCH_ATLAS6
|
|
bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
|
|
default y
|
|
select SIRF_IRQ
|
|
help
|
|
Support for CSR SiRFSoC ARM Cortex A9 Platform
|
|
|
|
config ARCH_ATLAS7
|
|
bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform"
|
|
default y
|
|
select ARM_GIC
|
|
select CPU_V7
|
|
select HAVE_ARM_SCU if SMP
|
|
select HAVE_SMP
|
|
help
|
|
Support for CSR SiRFSoC ARM Cortex A7 Platform
|
|
|
|
config ARCH_PRIMA2
|
|
bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
|
|
default y
|
|
select SIRF_IRQ
|
|
select ZONE_DMA
|
|
help
|
|
Support for CSR SiRFSoC ARM Cortex A9 Platform
|
|
|
|
config SIRF_IRQ
|
|
bool
|
|
|
|
endif
|