linux_dsm_epyc7002/arch/mips
Wu Zhangjin 4e73238d16 MIPS: Oprofile: Fix Loongson irq handler
The interrupt enable bit for the performance counters is in the Control
    Register $24, not in the counter register.
    loongson2_perfcount_handler(), we need to use
    
    Reported-by: Xu Hengyang <hengyang@mail.ustc.edu.cn>
    Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: http://patchwork.linux-mips.org/patch/1198/
    Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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2010-05-15 21:59:54 +01:00
..
alchemy
ar7
bcm47xx
bcm63xx
boot
cavium-octeon
cobalt
configs
dec
emma
fw
gt64120/wrppmc
include/asm MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1 2010-05-15 21:59:53 +01:00
jazz
kernel MIPS: N32: Use compat version for sys_ppoll. 2010-05-15 21:59:53 +01:00
lasat
lib
loongson MIPS: Loongson 2F: Fix of problems introduced by -mfix-loongson2f-jump 2010-04-30 20:52:58 +01:00
math-emu MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1 2010-05-15 21:59:53 +01:00
mipssim
mm
mti-malta
nxp
oprofile MIPS: Oprofile: Fix Loongson irq handler 2010-05-15 21:59:54 +01:00
pci
pmc-sierra
power
powertv
rb532
sgi-ip22
sgi-ip27
sgi-ip32
sibyte
sni
txx9
vr41xx
Kconfig MIPS: Loongson: Add CPU_LOONGSON2F_WORKAROUNDS 2010-04-30 20:52:56 +01:00
Kconfig.debug
Makefile MIPS: Loongson 2F: Enable fixups of the latest binutils 2010-04-30 20:52:56 +01:00