mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
019f34fccf
Well, instead of having a real bank 4 on the BSP of each node and symlinks on the remaining cores, we push it up into the amd_northbridge descriptor which now contains a pointer to the northbridge bank 4 because the bank is one per northbridge and, as such, belongs in the NB descriptor anyway. Each time we hotplug CPUs, we use the northbridge pointer to copy the shared bank into the per-CPU array of threshold_banks pointers, or destroy it when the last CPU on the node goes offline, or create it when the first comes online. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
94 lines
1.9 KiB
C
94 lines
1.9 KiB
C
#ifndef _ASM_X86_AMD_NB_H
|
|
#define _ASM_X86_AMD_NB_H
|
|
|
|
#include <linux/ioport.h>
|
|
#include <linux/pci.h>
|
|
|
|
struct amd_nb_bus_dev_range {
|
|
u8 bus;
|
|
u8 dev_base;
|
|
u8 dev_limit;
|
|
};
|
|
|
|
extern const struct pci_device_id amd_nb_misc_ids[];
|
|
extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
|
|
|
|
extern bool early_is_amd_nb(u32 value);
|
|
extern struct resource *amd_get_mmconfig_range(struct resource *res);
|
|
extern int amd_cache_northbridges(void);
|
|
extern void amd_flush_garts(void);
|
|
extern int amd_numa_init(void);
|
|
extern int amd_get_subcaches(int);
|
|
extern int amd_set_subcaches(int, int);
|
|
|
|
struct amd_l3_cache {
|
|
unsigned indices;
|
|
u8 subcaches[4];
|
|
};
|
|
|
|
struct threshold_block {
|
|
unsigned int block;
|
|
unsigned int bank;
|
|
unsigned int cpu;
|
|
u32 address;
|
|
u16 interrupt_enable;
|
|
bool interrupt_capable;
|
|
u16 threshold_limit;
|
|
struct kobject kobj;
|
|
struct list_head miscj;
|
|
};
|
|
|
|
struct threshold_bank {
|
|
struct kobject *kobj;
|
|
struct threshold_block *blocks;
|
|
|
|
/* initialized to the number of CPUs on the node sharing this bank */
|
|
atomic_t cpus;
|
|
};
|
|
|
|
struct amd_northbridge {
|
|
struct pci_dev *misc;
|
|
struct pci_dev *link;
|
|
struct amd_l3_cache l3_cache;
|
|
struct threshold_bank *bank4;
|
|
};
|
|
|
|
struct amd_northbridge_info {
|
|
u16 num;
|
|
u64 flags;
|
|
struct amd_northbridge *nb;
|
|
};
|
|
extern struct amd_northbridge_info amd_northbridges;
|
|
|
|
#define AMD_NB_GART BIT(0)
|
|
#define AMD_NB_L3_INDEX_DISABLE BIT(1)
|
|
#define AMD_NB_L3_PARTITIONING BIT(2)
|
|
|
|
#ifdef CONFIG_AMD_NB
|
|
|
|
static inline u16 amd_nb_num(void)
|
|
{
|
|
return amd_northbridges.num;
|
|
}
|
|
|
|
static inline bool amd_nb_has_feature(unsigned feature)
|
|
{
|
|
return ((amd_northbridges.flags & feature) == feature);
|
|
}
|
|
|
|
static inline struct amd_northbridge *node_to_amd_nb(int node)
|
|
{
|
|
return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
|
|
}
|
|
|
|
#else
|
|
|
|
#define amd_nb_num(x) 0
|
|
#define amd_nb_has_feature(x) false
|
|
#define node_to_amd_nb(x) NULL
|
|
|
|
#endif
|
|
|
|
|
|
#endif /* _ASM_X86_AMD_NB_H */
|