mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
c6fe9a2edf
The NAND controller on NS2 SoC is compatible with existing BRCM IPROC NAND driver so let's enable it in NS2 DT and NS2 SVK DT. This patch also fixes use of node labels in ns2-svk.dts. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Reviewed-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
231 lines
6.7 KiB
Plaintext
231 lines
6.7 KiB
Plaintext
/*
|
|
* BSD LICENSE
|
|
*
|
|
* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
*
|
|
* * Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* * Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in
|
|
* the documentation and/or other materials provided with the
|
|
* distribution.
|
|
* * Neither the name of Broadcom Corporation nor the names of its
|
|
* contributors may be used to endorse or promote products derived
|
|
* from this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
/memreserve/ 0x84b00000 0x00000008;
|
|
|
|
/ {
|
|
compatible = "brcm,ns2";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
cpus {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
A57_0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57", "arm,armv8";
|
|
reg = <0 0>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0 0x84b00000>;
|
|
next-level-cache = <&CLUSTER0_L2>;
|
|
};
|
|
|
|
A57_1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57", "arm,armv8";
|
|
reg = <0 1>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0 0x84b00000>;
|
|
next-level-cache = <&CLUSTER0_L2>;
|
|
};
|
|
|
|
A57_2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57", "arm,armv8";
|
|
reg = <0 2>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0 0x84b00000>;
|
|
next-level-cache = <&CLUSTER0_L2>;
|
|
};
|
|
|
|
A57_3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a57", "arm,armv8";
|
|
reg = <0 3>;
|
|
enable-method = "spin-table";
|
|
cpu-release-addr = <0 0x84b00000>;
|
|
next-level-cache = <&CLUSTER0_L2>;
|
|
};
|
|
|
|
CLUSTER0_L2: l2-cache@000 {
|
|
compatible = "cache";
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
|
|
IRQ_TYPE_EDGE_RISING)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
|
|
IRQ_TYPE_EDGE_RISING)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
|
|
IRQ_TYPE_EDGE_RISING)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
|
|
IRQ_TYPE_EDGE_RISING)>;
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-affinity = <&A57_0>,
|
|
<&A57_1>,
|
|
<&A57_2>,
|
|
<&A57_3>;
|
|
};
|
|
|
|
soc: soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
|
|
smmu: mmu@64000000 {
|
|
compatible = "arm,mmu-500";
|
|
reg = <0x64000000 0x40000>;
|
|
#global-interrupts = <2>;
|
|
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
|
|
mmu-masters;
|
|
};
|
|
|
|
crmu: crmu@65024000 {
|
|
compatible = "syscon";
|
|
reg = <0x65024000 0x100>;
|
|
};
|
|
|
|
reboot@65024000 {
|
|
compatible ="syscon-reboot";
|
|
regmap = <&crmu>;
|
|
offset = <0x90>;
|
|
mask = <0xfffffffd>;
|
|
};
|
|
|
|
gic: interrupt-controller@65210000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
reg = <0x65210000 0x1000>,
|
|
<0x65220000 0x1000>,
|
|
<0x65240000 0x2000>,
|
|
<0x65260000 0x1000>;
|
|
};
|
|
|
|
i2c0: i2c@66080000 {
|
|
compatible = "brcm,iproc-i2c";
|
|
reg = <0x66080000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
|
|
clock-frequency = <100000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@660b0000 {
|
|
compatible = "brcm,iproc-i2c";
|
|
reg = <0x660b0000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
|
|
clock-frequency = <100000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@66130000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x66130000 0x100>;
|
|
interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clock-frequency = <23961600>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hwrng: hwrng@66220000 {
|
|
compatible = "brcm,iproc-rng200";
|
|
reg = <0x66220000 0x28>;
|
|
};
|
|
|
|
nand: nand@66460000 {
|
|
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
|
|
reg = <0x66460000 0x600>,
|
|
<0x67015408 0x600>,
|
|
<0x66460f00 0x20>;
|
|
reg-names = "nand", "iproc-idm", "iproc-ext";
|
|
interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
brcm,nand-has-wp;
|
|
};
|
|
};
|
|
};
|