mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 00:35:35 +07:00
1849f800fb
Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
New machines:
- The new Action Semi S500 platform is added along with initial
support for the LeMaker Guitar board.
- STM32 gains support for three new boards: stm32h743-disco,
stm32f746-disco, and stm32f769-disco, along with new device
support for the existing stm32f429 boards.
- Renesas adds two new boards, the tiny GR-Peach based on RZ/A1H
with 10MB on-chip SRAM, and the iWave G20D-Q7 System-on-Module
plus board.
- On Marvell "mvebu", we gain support for the Linksys WRT3200ACM
wireless router.
- For NXP i.MX, we gain support for the Gateworks Ventana GW5600
and the Technexion Pico i.MX7D single-board computers.
- The BeagleBone Blue is added for OMAP, it's the latest variation
of the popular Beaglebone Black single-board computer.
- The Allwinner based Lichee Pi Zero and NanoPi M1 Plus boards
are added, these are the latest variations of a seemingly endless
supply of similar single-board computers.
Other updates:
- Linus Walleij improves support for the "Faraday" based SoC platforms
from various SoC makers (Moxart, Aspeed, Gemini)
- The ARM Mali GPU is now describe on Rockchips SoCs
- Mediatek MT7623 is extended significantly, making it much
more useful.
- Lots of individual updates on Renesas, OMAP, Rockchips, Broadcom,
Allwinner, Qualcomm, iMX
- For Amlogic, the clock support is extended a lot on meson8b.
- We now build the devicetree file for the Raspberry Pi 3 on 32-bit
ARM, in addition to the existing ARM64 support, to help users
wanting to run a 32-bit system on it.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM device-tree updates from Arnd Bergmann:
"Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
New machines:
- The new Action Semi S500 platform is added along with initial
support for the LeMaker Guitar board.
- STM32 gains support for three new boards: stm32h743-disco,
stm32f746-disco, and stm32f769-disco, along with new device support
for the existing stm32f429 boards.
- Renesas adds two new boards, the tiny GR-Peach based on RZ/A1H with
10MB on-chip SRAM, and the iWave G20D-Q7 System-on-Module plus
board.
- On Marvell "mvebu", we gain support for the Linksys WRT3200ACM
wireless router.
- For NXP i.MX, we gain support for the Gateworks Ventana GW5600 and
the Technexion Pico i.MX7D single-board computers.
- The BeagleBone Blue is added for OMAP, it's the latest variation of
the popular Beaglebone Black single-board computer.
- The Allwinner based Lichee Pi Zero and NanoPi M1 Plus boards are
added, these are the latest variations of a seemingly endless
supply of similar single-board computers.
Other updates:
- Linus Walleij improves support for the "Faraday" based SoC
platforms from various SoC makers (Moxart, Aspeed, Gemini)
- The ARM Mali GPU is now describe on Rockchips SoCs
- Mediatek MT7623 is extended significantly, making it much more
useful.
- Lots of individual updates on Renesas, OMAP, Rockchips, Broadcom,
Allwinner, Qualcomm, iMX
- For Amlogic, the clock support is extended a lot on meson8b.
- We now build the devicetree file for the Raspberry Pi 3 on 32-bit
ARM, in addition to the existing ARM64 support, to help users
wanting to run a 32-bit system on it"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (345 commits)
ARM: dts: socfpga: set the i2c frequency
ARM: dts: socfpga: Add second ethernet alias to VINING FPGA
ARM: dts: socfpga: Drop LED node from VINING FPGA
ARM: dts: socfpga: Remove I2C EEPROMs from VINING FPGA
ARM: dts: socfpga: Enable QSPI support on VINING FPGA
ARM: dts: socfpga: Fix the ethernet clock phandle
ARM: pxa: Use - instead of @ for DT OPP entries
ARM: dts: owl-s500: Add SPS node
ARM: dts: owl-s500: Set CPU enable-method
dt-bindings: arm: cpus: Add S500 enable-method
ARM: dts: Add Actions Semi S500 and LeMaker Guitar
dt-bindings: arm: Document Actions Semi S900
dt-bindings: timer: Document Owl timer
ARM: dts: imx6q-cm-fx6: add sdio wifi/bt nodes
dt-bindings: arm: Document Actions Semi S500
dt-bindings: Add vendor prefix for Actions Semi
ARM: dts: turris-omnia: Add generic compatible string for I2C EEPROM
ARM: dts: mvebu: add support for Linksys WRT3200ACM (Rango)
ARM: dts: armada-385-linksys: fixup button node names
ARM: dts: armada-385-linksys: group pins in pinctrl
...
639 lines
15 KiB
Plaintext
639 lines
15 KiB
Plaintext
#include <dt-bindings/pinctrl/bcm2835.h>
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#include <dt-bindings/clock/bcm2835.h>
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#include <dt-bindings/clock/bcm2835-aux.h>
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#include <dt-bindings/gpio/gpio.h>
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/* firmware-provided startup stubs live here, where the secondary CPUs are
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* spinning.
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*/
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/memreserve/ 0x00000000 0x00001000;
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/* This include file covers the common peripherals and configuration between
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* bcm2835 and bcm2836 implementations, leaving the CPU configuration to
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* bcm2835.dtsi and bcm2836.dtsi.
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*/
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/ {
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compatible = "brcm,bcm2835";
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model = "BCM2835";
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interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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bootargs = "earlyprintk console=ttyAMA0";
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <0>;
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polling-delay = <1000>;
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thermal-sensors = <&thermal>;
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trips {
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cpu-crit {
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temperature = <80000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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};
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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timer@7e003000 {
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compatible = "brcm,bcm2835-system-timer";
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reg = <0x7e003000 0x1000>;
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interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
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/* This could be a reference to BCM2835_CLOCK_TIMER,
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* but we don't have the driver using the common clock
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* support yet.
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*/
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clock-frequency = <1000000>;
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};
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dma: dma@7e007000 {
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compatible = "brcm,bcm2835-dma";
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reg = <0x7e007000 0xf00>;
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interrupts = <1 16>,
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<1 17>,
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<1 18>,
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<1 19>,
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<1 20>,
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<1 21>,
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<1 22>,
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<1 23>,
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<1 24>,
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<1 25>,
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<1 26>,
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/* dma channel 11-14 share one irq */
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<1 27>,
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<1 27>,
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<1 27>,
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<1 27>,
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/* unused shared irq for all channels */
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<1 28>;
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interrupt-names = "dma0",
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"dma1",
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"dma2",
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"dma3",
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"dma4",
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"dma5",
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"dma6",
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"dma7",
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"dma8",
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"dma9",
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"dma10",
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"dma11",
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"dma12",
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"dma13",
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"dma14",
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"dma-shared-all";
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#dma-cells = <1>;
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brcm,dma-channel-mask = <0x7f35>;
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};
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intc: interrupt-controller@7e00b200 {
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compatible = "brcm,bcm2835-armctrl-ic";
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reg = <0x7e00b200 0x200>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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watchdog@7e100000 {
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compatible = "brcm,bcm2835-pm-wdt";
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reg = <0x7e100000 0x28>;
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};
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clocks: cprman@7e101000 {
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compatible = "brcm,bcm2835-cprman";
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#clock-cells = <1>;
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reg = <0x7e101000 0x2000>;
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/* CPRMAN derives almost everything from the
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* platform's oscillator. However, the DSI
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* pixel clocks come from the DSI analog PHY.
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*/
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clocks = <&clk_osc>,
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<&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
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<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
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};
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rng@7e104000 {
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compatible = "brcm,bcm2835-rng";
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reg = <0x7e104000 0x10>;
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};
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mailbox: mailbox@7e00b880 {
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compatible = "brcm,bcm2835-mbox";
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reg = <0x7e00b880 0x40>;
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interrupts = <0 1>;
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#mbox-cells = <0>;
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};
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gpio: gpio@7e200000 {
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compatible = "brcm,bcm2835-gpio";
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reg = <0x7e200000 0xb4>;
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/*
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* The GPIO IP block is designed for 3 banks of GPIOs.
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* Each bank has a GPIO interrupt for itself.
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* There is an overall "any bank" interrupt.
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* In order, these are GIC interrupts 17, 18, 19, 20.
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* Since the BCM2835 only has 2 banks, the 2nd bank
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* interrupt output appears to be mirrored onto the
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* 3rd bank's interrupt signal.
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* So, a bank0 interrupt shows up on 17, 20, and
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* a bank1 interrupt shows up on 18, 19, 20!
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*/
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interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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/* Defines pin muxing groups according to
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* BCM2835-ARM-Peripherals.pdf page 102.
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*
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* While each pin can have its mux selected
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* for various functions individually, some
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* groups only make sense to switch to a
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* particular function together.
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*/
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dpi_gpio0: dpi_gpio0 {
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brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
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12 13 14 15 16 17 18 19
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20 21 22 23 24 25 26 27>;
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brcm,function = <BCM2835_FSEL_ALT2>;
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};
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emmc_gpio22: emmc_gpio22 {
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brcm,pins = <22 23 24 25 26 27>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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};
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emmc_gpio34: emmc_gpio34 {
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brcm,pins = <34 35 36 37 38 39>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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brcm,pull = <BCM2835_PUD_OFF
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BCM2835_PUD_UP
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BCM2835_PUD_UP
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BCM2835_PUD_UP
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BCM2835_PUD_UP
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BCM2835_PUD_UP>;
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};
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emmc_gpio48: emmc_gpio48 {
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brcm,pins = <48 49 50 51 52 53>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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};
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gpclk0_gpio4: gpclk0_gpio4 {
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brcm,pins = <4>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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gpclk1_gpio5: gpclk1_gpio5 {
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brcm,pins = <5>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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gpclk1_gpio42: gpclk1_gpio42 {
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brcm,pins = <42>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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gpclk1_gpio44: gpclk1_gpio44 {
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brcm,pins = <44>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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gpclk2_gpio6: gpclk2_gpio6 {
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brcm,pins = <6>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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gpclk2_gpio43: gpclk2_gpio43 {
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brcm,pins = <43>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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i2c0_gpio0: i2c0_gpio0 {
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brcm,pins = <0 1>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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i2c0_gpio28: i2c0_gpio28 {
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brcm,pins = <28 29>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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i2c0_gpio44: i2c0_gpio44 {
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brcm,pins = <44 45>;
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brcm,function = <BCM2835_FSEL_ALT1>;
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};
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i2c1_gpio2: i2c1_gpio2 {
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brcm,pins = <2 3>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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i2c1_gpio44: i2c1_gpio44 {
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brcm,pins = <44 45>;
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brcm,function = <BCM2835_FSEL_ALT2>;
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};
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i2c_slave_gpio18: i2c_slave_gpio18 {
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brcm,pins = <18 19 20 21>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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};
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jtag_gpio4: jtag_gpio4 {
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brcm,pins = <4 5 6 12 13>;
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brcm,function = <BCM2835_FSEL_ALT4>;
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};
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jtag_gpio22: jtag_gpio22 {
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brcm,pins = <22 23 24 25 26 27>;
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brcm,function = <BCM2835_FSEL_ALT4>;
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};
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pcm_gpio18: pcm_gpio18 {
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brcm,pins = <18 19 20 21>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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pcm_gpio28: pcm_gpio28 {
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brcm,pins = <28 29 30 31>;
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brcm,function = <BCM2835_FSEL_ALT2>;
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};
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pwm0_gpio12: pwm0_gpio12 {
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brcm,pins = <12>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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pwm0_gpio18: pwm0_gpio18 {
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brcm,pins = <18>;
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brcm,function = <BCM2835_FSEL_ALT5>;
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};
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pwm0_gpio40: pwm0_gpio40 {
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brcm,pins = <40>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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pwm1_gpio13: pwm1_gpio13 {
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brcm,pins = <13>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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pwm1_gpio19: pwm1_gpio19 {
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brcm,pins = <19>;
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brcm,function = <BCM2835_FSEL_ALT5>;
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};
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pwm1_gpio41: pwm1_gpio41 {
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brcm,pins = <41>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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pwm1_gpio45: pwm1_gpio45 {
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brcm,pins = <45>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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sdhost_gpio48: sdhost_gpio48 {
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brcm,pins = <48 49 50 51 52 53>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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spi0_gpio7: spi0_gpio7 {
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brcm,pins = <7 8 9 10 11>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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spi0_gpio35: spi0_gpio35 {
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brcm,pins = <35 36 37 38 39>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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spi1_gpio16: spi1_gpio16 {
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brcm,pins = <16 17 18 19 20 21>;
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brcm,function = <BCM2835_FSEL_ALT4>;
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};
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spi2_gpio40: spi2_gpio40 {
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brcm,pins = <40 41 42 43 44 45>;
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brcm,function = <BCM2835_FSEL_ALT4>;
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};
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uart0_gpio14: uart0_gpio14 {
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brcm,pins = <14 15>;
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brcm,function = <BCM2835_FSEL_ALT0>;
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};
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/* Separate from the uart0_gpio14 group
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* because it conflicts with spi1_gpio16, and
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* people often run uart0 on the two pins
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* without flow control.
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*/
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uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
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brcm,pins = <16 17>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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};
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uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
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brcm,pins = <30 31>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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};
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uart0_gpio32: uart0_gpio32 {
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brcm,pins = <32 33>;
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brcm,function = <BCM2835_FSEL_ALT3>;
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};
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uart0_gpio36: uart0_gpio36 {
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brcm,pins = <36 37>;
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brcm,function = <BCM2835_FSEL_ALT2>;
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};
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uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
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brcm,pins = <38 39>;
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brcm,function = <BCM2835_FSEL_ALT2>;
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};
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uart1_gpio14: uart1_gpio14 {
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brcm,pins = <14 15>;
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brcm,function = <BCM2835_FSEL_ALT5>;
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};
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uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
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brcm,pins = <16 17>;
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brcm,function = <BCM2835_FSEL_ALT5>;
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};
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uart1_gpio32: uart1_gpio32 {
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brcm,pins = <32 33>;
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brcm,function = <BCM2835_FSEL_ALT5>;
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};
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uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
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brcm,pins = <30 31>;
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brcm,function = <BCM2835_FSEL_ALT5>;
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};
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uart1_gpio40: uart1_gpio40 {
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brcm,pins = <40 41>;
|
|
brcm,function = <BCM2835_FSEL_ALT5>;
|
|
};
|
|
uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
|
|
brcm,pins = <42 43>;
|
|
brcm,function = <BCM2835_FSEL_ALT5>;
|
|
};
|
|
};
|
|
|
|
uart0: serial@7e201000 {
|
|
compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
|
|
reg = <0x7e201000 0x1000>;
|
|
interrupts = <2 25>;
|
|
clocks = <&clocks BCM2835_CLOCK_UART>,
|
|
<&clocks BCM2835_CLOCK_VPU>;
|
|
clock-names = "uartclk", "apb_pclk";
|
|
arm,primecell-periphid = <0x00241011>;
|
|
};
|
|
|
|
sdhost: mmc@7e202000 {
|
|
compatible = "brcm,bcm2835-sdhost";
|
|
reg = <0x7e202000 0x100>;
|
|
interrupts = <2 24>;
|
|
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
dmas = <&dma 13>;
|
|
dma-names = "rx-tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s: i2s@7e203000 {
|
|
compatible = "brcm,bcm2835-i2s";
|
|
reg = <0x7e203000 0x20>,
|
|
<0x7e101098 0x02>;
|
|
|
|
dmas = <&dma 2>,
|
|
<&dma 3>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi: spi@7e204000 {
|
|
compatible = "brcm,bcm2835-spi";
|
|
reg = <0x7e204000 0x1000>;
|
|
interrupts = <2 22>;
|
|
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@7e205000 {
|
|
compatible = "brcm,bcm2835-i2c";
|
|
reg = <0x7e205000 0x1000>;
|
|
interrupts = <2 21>;
|
|
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pixelvalve@7e206000 {
|
|
compatible = "brcm,bcm2835-pixelvalve0";
|
|
reg = <0x7e206000 0x100>;
|
|
interrupts = <2 13>; /* pwa0 */
|
|
};
|
|
|
|
pixelvalve@7e207000 {
|
|
compatible = "brcm,bcm2835-pixelvalve1";
|
|
reg = <0x7e207000 0x100>;
|
|
interrupts = <2 14>; /* pwa1 */
|
|
};
|
|
|
|
dsi0: dsi@7e209000 {
|
|
compatible = "brcm,bcm2835-dsi0";
|
|
reg = <0x7e209000 0x78>;
|
|
interrupts = <2 4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#clock-cells = <1>;
|
|
|
|
clocks = <&clocks BCM2835_PLLA_DSI0>,
|
|
<&clocks BCM2835_CLOCK_DSI0E>,
|
|
<&clocks BCM2835_CLOCK_DSI0P>;
|
|
clock-names = "phy", "escape", "pixel";
|
|
|
|
clock-output-names = "dsi0_byte",
|
|
"dsi0_ddr2",
|
|
"dsi0_ddr";
|
|
|
|
};
|
|
|
|
thermal: thermal@7e212000 {
|
|
compatible = "brcm,bcm2835-thermal";
|
|
reg = <0x7e212000 0x8>;
|
|
clocks = <&clocks BCM2835_CLOCK_TSENS>;
|
|
#thermal-sensor-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
aux: aux@0x7e215000 {
|
|
compatible = "brcm,bcm2835-aux";
|
|
#clock-cells = <1>;
|
|
reg = <0x7e215000 0x8>;
|
|
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
};
|
|
|
|
uart1: serial@7e215040 {
|
|
compatible = "brcm,bcm2835-aux-uart";
|
|
reg = <0x7e215040 0x40>;
|
|
interrupts = <1 29>;
|
|
clocks = <&aux BCM2835_AUX_CLOCK_UART>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@7e215080 {
|
|
compatible = "brcm,bcm2835-aux-spi";
|
|
reg = <0x7e215080 0x40>;
|
|
interrupts = <1 29>;
|
|
clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@7e2150c0 {
|
|
compatible = "brcm,bcm2835-aux-spi";
|
|
reg = <0x7e2150c0 0x40>;
|
|
interrupts = <1 29>;
|
|
clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@7e20c000 {
|
|
compatible = "brcm,bcm2835-pwm";
|
|
reg = <0x7e20c000 0x28>;
|
|
clocks = <&clocks BCM2835_CLOCK_PWM>;
|
|
assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
|
|
assigned-clock-rates = <10000000>;
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci: sdhci@7e300000 {
|
|
compatible = "brcm,bcm2835-sdhci";
|
|
reg = <0x7e300000 0x100>;
|
|
interrupts = <2 30>;
|
|
clocks = <&clocks BCM2835_CLOCK_EMMC>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hvs@7e400000 {
|
|
compatible = "brcm,bcm2835-hvs";
|
|
reg = <0x7e400000 0x6000>;
|
|
interrupts = <2 1>;
|
|
};
|
|
|
|
dsi1: dsi@7e700000 {
|
|
compatible = "brcm,bcm2835-dsi1";
|
|
reg = <0x7e700000 0x8c>;
|
|
interrupts = <2 12>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#clock-cells = <1>;
|
|
|
|
clocks = <&clocks BCM2835_PLLD_DSI1>,
|
|
<&clocks BCM2835_CLOCK_DSI1E>,
|
|
<&clocks BCM2835_CLOCK_DSI1P>;
|
|
clock-names = "phy", "escape", "pixel";
|
|
|
|
clock-output-names = "dsi1_byte",
|
|
"dsi1_ddr2",
|
|
"dsi1_ddr";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@7e804000 {
|
|
compatible = "brcm,bcm2835-i2c";
|
|
reg = <0x7e804000 0x1000>;
|
|
interrupts = <2 21>;
|
|
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@7e805000 {
|
|
compatible = "brcm,bcm2835-i2c";
|
|
reg = <0x7e805000 0x1000>;
|
|
interrupts = <2 21>;
|
|
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vec: vec@7e806000 {
|
|
compatible = "brcm,bcm2835-vec";
|
|
reg = <0x7e806000 0x1000>;
|
|
clocks = <&clocks BCM2835_CLOCK_VEC>;
|
|
interrupts = <2 27>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pixelvalve@7e807000 {
|
|
compatible = "brcm,bcm2835-pixelvalve2";
|
|
reg = <0x7e807000 0x100>;
|
|
interrupts = <2 10>; /* pixelvalve */
|
|
};
|
|
|
|
hdmi: hdmi@7e902000 {
|
|
compatible = "brcm,bcm2835-hdmi";
|
|
reg = <0x7e902000 0x600>,
|
|
<0x7e808000 0x100>;
|
|
interrupts = <2 8>, <2 9>;
|
|
ddc = <&i2c2>;
|
|
clocks = <&clocks BCM2835_PLLH_PIX>,
|
|
<&clocks BCM2835_CLOCK_HSM>;
|
|
clock-names = "pixel", "hdmi";
|
|
dmas = <&dma 17>;
|
|
dma-names = "audio-rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb: usb@7e980000 {
|
|
compatible = "brcm,bcm2835-usb";
|
|
reg = <0x7e980000 0x10000>;
|
|
interrupts = <1 9>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clk_usb>;
|
|
clock-names = "otg";
|
|
phys = <&usbphy>;
|
|
phy-names = "usb2-phy";
|
|
};
|
|
|
|
v3d: v3d@7ec00000 {
|
|
compatible = "brcm,bcm2835-v3d";
|
|
reg = <0x7ec00000 0x1000>;
|
|
interrupts = <1 10>;
|
|
};
|
|
|
|
vc4: gpu {
|
|
compatible = "brcm,bcm2835-vc4";
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
/* The oscillator is the root of the clock tree. */
|
|
clk_osc: clock@3 {
|
|
compatible = "fixed-clock";
|
|
reg = <3>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "osc";
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
clk_usb: clock@4 {
|
|
compatible = "fixed-clock";
|
|
reg = <4>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "otg";
|
|
clock-frequency = <480000000>;
|
|
};
|
|
};
|
|
|
|
usbphy: phy {
|
|
compatible = "usb-nop-xceiv";
|
|
};
|
|
};
|