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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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77612720a2
When the Hfplls are reprogrammed during the rate change, the primary muxes which are sourced from the same hfpll for higher frequencies, needs to be switched to the 'safe secondary mux' as the parent for that small window. This is done by registering a clk notifier for the muxes and switching to the safe parent in the PRE_RATE_CHANGE notifier and back to the original parent in the POST_RATE_CHANGE notifier. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
127 lines
3.2 KiB
C
127 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/clk-provider.h>
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#include <linux/spinlock.h>
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#include <asm/krait-l2-accessors.h>
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#include "clk-krait.h"
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/* Secondary and primary muxes share the same cp15 register */
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static DEFINE_SPINLOCK(krait_clock_reg_lock);
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#define LPL_SHIFT 8
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static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
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{
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unsigned long flags;
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u32 regval;
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spin_lock_irqsave(&krait_clock_reg_lock, flags);
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regval = krait_get_l2_indirect_reg(mux->offset);
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regval &= ~(mux->mask << mux->shift);
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regval |= (sel & mux->mask) << mux->shift;
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if (mux->lpl) {
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regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
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regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
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}
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krait_set_l2_indirect_reg(mux->offset, regval);
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spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
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/* Wait for switch to complete. */
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mb();
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udelay(1);
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}
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static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct krait_mux_clk *mux = to_krait_mux_clk(hw);
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u32 sel;
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sel = clk_mux_index_to_val(mux->parent_map, 0, index);
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mux->en_mask = sel;
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/* Don't touch mux if CPU is off as it won't work */
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if (__clk_is_enabled(hw->clk))
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__krait_mux_set_sel(mux, sel);
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mux->reparent = true;
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return 0;
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}
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static u8 krait_mux_get_parent(struct clk_hw *hw)
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{
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struct krait_mux_clk *mux = to_krait_mux_clk(hw);
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u32 sel;
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sel = krait_get_l2_indirect_reg(mux->offset);
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sel >>= mux->shift;
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sel &= mux->mask;
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mux->en_mask = sel;
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return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
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}
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const struct clk_ops krait_mux_clk_ops = {
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.set_parent = krait_mux_set_parent,
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.get_parent = krait_mux_get_parent,
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.determine_rate = __clk_mux_determine_rate_closest,
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};
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EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
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/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
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static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
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return DIV_ROUND_UP(*parent_rate, 2);
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}
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static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct krait_div2_clk *d = to_krait_div2_clk(hw);
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unsigned long flags;
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u32 val;
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u32 mask = BIT(d->width) - 1;
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if (d->lpl)
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mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
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spin_lock_irqsave(&krait_clock_reg_lock, flags);
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val = krait_get_l2_indirect_reg(d->offset);
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val &= ~mask;
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krait_set_l2_indirect_reg(d->offset, val);
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spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
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return 0;
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}
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static unsigned long
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krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct krait_div2_clk *d = to_krait_div2_clk(hw);
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u32 mask = BIT(d->width) - 1;
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u32 div;
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div = krait_get_l2_indirect_reg(d->offset);
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div >>= d->shift;
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div &= mask;
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div = (div + 1) * 2;
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return DIV_ROUND_UP(parent_rate, div);
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}
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const struct clk_ops krait_div2_clk_ops = {
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.round_rate = krait_div2_round_rate,
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.set_rate = krait_div2_set_rate,
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.recalc_rate = krait_div2_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
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