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6f357de854
Add DT bindings for NAND devices connected to the NEMC on JZ4780 SoCs,
as well as the hardware BCH controller, used by the jz4780_{nand,bch}
drivers.
Signed-off-by: Alex Smith <alex.smith@imgtec.com>
Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: linux-mtd@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
87 lines
2.5 KiB
Plaintext
87 lines
2.5 KiB
Plaintext
* Ingenic JZ4780 NAND/BCH
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This file documents the device tree bindings for NAND flash devices on the
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JZ4780. NAND devices are connected to the NEMC controller (described in
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memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
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be children of the NEMC node.
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Required NAND controller device properties:
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- compatible: Should be set to "ingenic,jz4780-nand".
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- reg: For each bank with a NAND chip attached, should specify a bank number,
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an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank).
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Optional NAND controller device properties:
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- ingenic,bch-controller: To make use of the hardware BCH controller, this
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property must contain a phandle for the BCH controller node. The required
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properties for this node are described below. If this is not specified,
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software BCH will be used instead.
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Optional children nodes:
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- Individual NAND chips are children of the NAND controller node.
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Required children node properties:
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- reg: An integer ranging from 1 to 6 representing the CS line to use.
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Optional children node properties:
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- nand-ecc-step-size: ECC block size in bytes.
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- nand-ecc-strength: ECC strength (max number of correctable bits).
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- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
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- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present false
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- rb-gpios: GPIO specifier for the busy pin.
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- wp-gpios: GPIO specifier for the write protect pin.
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Optional child node of NAND chip nodes:
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- partitions: see Documentation/devicetree/bindings/mtd/partition.txt
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Example:
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nemc: nemc@13410000 {
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...
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nandc: nand-controller@1 {
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compatible = "ingenic,jz4780-nand";
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reg = <1 0 0x1000000>; /* Bank 1 */
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#address-cells = <1>;
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#size-cells = <0>;
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ingenic,bch-controller = <&bch>;
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nand@1 {
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reg = <1>;
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nand-ecc-step-size = <1024>;
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nand-ecc-strength = <24>;
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nand-ecc-mode = "hw";
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nand-on-flash-bbt;
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rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;
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partitions {
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#address-cells = <2>;
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#size-cells = <2>;
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...
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}
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};
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};
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};
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The BCH controller is a separate SoC component used for error correction on
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NAND devices. The following is a description of the device properties for a
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BCH controller.
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Required BCH properties:
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- compatible: Should be set to "ingenic,jz4780-bch".
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- reg: Should specify the BCH controller registers location and length.
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- clocks: Clock for the BCH controller.
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Example:
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bch: bch@134d0000 {
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compatible = "ingenic,jz4780-bch";
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reg = <0x134d0000 0x10000>;
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clocks = <&cgu JZ4780_CLK_BCH>;
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};
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