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46febc6366
The latest Marvell bootloaders for various boards change the MBus Window base address from 0xC0000000 to 0xF0000000, in order to make more RAM in the first 4 GB actually usable by the kernel (RAM that is covered by the MBus window is "shadowed" and therefore not usable). However, our default PCIe memory and I/O apertures where sitting at 0xe0000000 (for memory) and 0xe8000000 (for I/O), which will now be outside of the MBus Window range on those platforms. To make things work, we have to ensure those apertures use addresses in the 0xF0000000 -> 0xFFFFFFFF range. Of course this change of the MBus Window base address from 0xC0000000 to 0xF0000000 also comes with a change of the internal register base address from 0xD0000000 to 0xF1000000. We have therefore designed the following memory map: * 0xF0000000 -> 0xF1000000: 16 MB, used for NOR flashes on Armada XP GP and Armada XP DB. * 0xF1000000 -> 0xF1100000: 1 MB, used for internal registers. * 0xF8000000 -> 0xFFE00000: 126 MB, used for PCIe memory. * 0xFFE00000 -> 0xFFF00000: 1 MB, used for PCIe I/O. * 0xFFF00000 -> 0xFFFFFFFF: 1 MB, used for the BootROM mapping There is one exception to this layout: the Armada XP OpenBlocks, which has a 128 MB NOR flash, mapped from 0xF0000000 to 0xF8000000. This does not conflict with the current change for the PCIe I/O and memory apertures, and continues to work because on Armada XP OpenBlocks, the bootloader is an old one, and continues to have internal registers mapped at 0xD0000000. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
285 lines
6.3 KiB
Plaintext
285 lines
6.3 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* This file contains the definitions that are common to the Armada
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* 370 and Armada XP SoC.
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*/
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/include/ "skeleton64.dtsi"
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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/ {
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model = "Marvell Armada 370 and XP SoC";
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compatible = "marvell,armada-370-xp";
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aliases {
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eth0 = ð0;
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eth1 = ð1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "marvell,sheeva-v7";
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device_type = "cpu";
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reg = <0>;
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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interrupt-parent = <&mpic>;
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pcie-mem-aperture = <0xf8000000 0x7e00000>;
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pcie-io-aperture = <0xffe00000 0x100000>;
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devbus-bootcs {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs0 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs1 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs2 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs3 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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internal-regs {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
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rtc@10300 {
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compatible = "marvell,orion-rtc";
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reg = <0x10300 0x20>;
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interrupts = <50>;
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};
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spi0: spi@10600 {
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compatible = "marvell,orion-spi";
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reg = <0x10600 0x28>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <30>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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spi1: spi@10680 {
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compatible = "marvell,orion-spi";
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reg = <0x10680 0x28>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <92>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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i2c0: i2c@11000 {
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compatible = "marvell,mv64xxx-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <31>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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i2c1: i2c@11100 {
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compatible = "marvell,mv64xxx-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <32>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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serial@12000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <41>;
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reg-io-width = <1>;
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status = "disabled";
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};
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serial@12100 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <42>;
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reg-io-width = <1>;
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status = "disabled";
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};
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coredivclk: corediv-clock@18740 {
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compatible = "marvell,armada-370-corediv-clock";
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reg = <0x18740 0xc>;
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#clock-cells = <1>;
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clocks = <&mainpll>;
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clock-output-names = "nand";
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};
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mbusc: mbus-controller@20000 {
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x100>, <0x20180 0x20>;
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};
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mpic: interrupt-controller@20000 {
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compatible = "marvell,mpic";
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#interrupt-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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msi-controller;
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};
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coherency-fabric@20200 {
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compatible = "marvell,coherency-fabric";
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reg = <0x20200 0xb0>, <0x21010 0x1c>;
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};
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timer@20300 {
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reg = <0x20300 0x30>, <0x21040 0x30>;
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interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
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};
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watchdog@20300 {
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reg = <0x20300 0x34>, <0x20704 0x4>;
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};
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usb@50000 {
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compatible = "marvell,orion-ehci";
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reg = <0x50000 0x500>;
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interrupts = <45>;
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status = "disabled";
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};
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usb@51000 {
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compatible = "marvell,orion-ehci";
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reg = <0x51000 0x500>;
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interrupts = <46>;
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status = "disabled";
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};
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eth0: ethernet@70000 {
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compatible = "marvell,armada-370-neta";
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reg = <0x70000 0x4000>;
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interrupts = <8>;
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clocks = <&gateclk 4>;
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status = "disabled";
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0x72004 0x4>;
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};
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eth1: ethernet@74000 {
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compatible = "marvell,armada-370-neta";
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reg = <0x74000 0x4000>;
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interrupts = <10>;
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clocks = <&gateclk 3>;
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status = "disabled";
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};
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sata@a0000 {
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compatible = "marvell,armada-370-sata";
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reg = <0xa0000 0x5000>;
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interrupts = <55>;
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clocks = <&gateclk 15>, <&gateclk 30>;
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clock-names = "0", "1";
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status = "disabled";
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};
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nand@d0000 {
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compatible = "marvell,armada370-nand";
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reg = <0xd0000 0x54>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupts = <113>;
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clocks = <&coredivclk 0>;
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status = "disabled";
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};
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mvsdio@d4000 {
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compatible = "marvell,orion-sdio";
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reg = <0xd4000 0x200>;
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interrupts = <54>;
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clocks = <&gateclk 17>;
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bus-width = <4>;
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cap-sdio-irq;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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status = "disabled";
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};
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};
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};
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clocks {
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/* 2 GHz fixed main PLL */
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mainpll: mainpll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <2000000000>;
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};
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};
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};
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