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The GCC_OFF_SMALL_ASM macro defines the constraint to use for
instructions needing "small offsets", typically the LL or SC
instructions. Historically these had 16 bit offsets, but microMIPS &
MIPS32/MIPS64r6 onwards reduced the width of the offset field.
GCC 4.9 & higher supports a ZC constraint which matches the offset
requirements of the LL & SC instructions. Where supported we can use
the ZC constraint regardless of ISA, and it will handle the requirements
of the ISA correctly. As such we require 3 cases:
- GCC 4.9 & higher can use ZC.
- GCC older than 4.9 must use the older R constraint, which does not
take into account microMIPS or MIPSr6.
- microMIPS builds therefore require GCC 4.9 or higher. MIPSr6 support
was only introduced in newer compilers anyway so it can be ignored
here.
The current code complicates this a little by specifically having MIPSr6
bypass the GCC version check, and using the R constraint for pre-MIPSr6
builds even if the compiler supports ZC which would be equivalent.
Simplify this such that the code straightforwardly implements the 3
cases outlined above.
For non-GCC compilers we presume that ZC is safe to use. In practice the
only non-GCC compiler of interest is clang and it has supported the ZC
constraint since version 3.7.0. It seems safe enough to presume that
nobody will expect to built a working kernel using a clang version older
than that, and if they do then they'll have bigger problems. As such we
don't check the clang version number & just presume ZC is usable when
the compiler is not GCC.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20999/
Cc: linux-mips@linux-mips.org
69 lines
2.7 KiB
C
69 lines
2.7 KiB
C
/*
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* Copyright (C) 2004, 2007 Maciej W. Rozycki
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef _ASM_COMPILER_H
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#define _ASM_COMPILER_H
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/*
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* With GCC 4.5 onwards we can use __builtin_unreachable to indicate to the
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* compiler that a particular code path will never be hit. This allows it to be
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* optimised out of the generated binary.
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*
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* Unfortunately at least GCC 4.6.3 through 7.3.0 inclusive suffer from a bug
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* that can lead to instructions from beyond an unreachable statement being
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* incorrectly reordered into earlier delay slots if the unreachable statement
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* is the only content of a case in a switch statement. This can lead to
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* seemingly random behaviour, such as invalid memory accesses from incorrectly
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* reordered loads or stores. See this potential GCC fix for details:
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*
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* https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00360.html
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*
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* It is unclear whether GCC 8 onwards suffer from the same issue - nothing
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* relevant is mentioned in GCC 8 release notes and nothing obviously relevant
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* stands out in GCC commit logs, but these newer GCC versions generate very
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* different code for the testcase which doesn't exhibit the bug.
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*
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* GCC also handles stack allocation suboptimally when calling noreturn
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* functions or calling __builtin_unreachable():
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*
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* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365
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*
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* We work around both of these issues by placing a volatile asm statement,
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* which GCC is prevented from reordering past, prior to __builtin_unreachable
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* calls.
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*
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* The .insn statement is required to ensure that any branches to the
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* statement, which sadly must be kept due to the asm statement, are known to
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* be branches to code and satisfy linker requirements for microMIPS kernels.
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*/
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#undef barrier_before_unreachable
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#define barrier_before_unreachable() asm volatile(".insn")
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#if !defined(CONFIG_CC_IS_GCC) || \
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(__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)
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# define GCC_OFF_SMALL_ASM() "ZC"
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#elif defined(CONFIG_CPU_MICROMIPS)
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# error "microMIPS compilation unsupported with GCC older than 4.9"
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#else
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# define GCC_OFF_SMALL_ASM() "R"
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#endif
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#ifdef CONFIG_CPU_MIPSR6
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#define MIPS_ISA_LEVEL "mips64r6"
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#define MIPS_ISA_ARCH_LEVEL MIPS_ISA_LEVEL
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#define MIPS_ISA_LEVEL_RAW mips64r6
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#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
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#else
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/* MIPS64 is a superset of MIPS32 */
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#define MIPS_ISA_LEVEL "mips64r2"
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#define MIPS_ISA_ARCH_LEVEL "arch=r4000"
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#define MIPS_ISA_LEVEL_RAW mips64r2
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#define MIPS_ISA_ARCH_LEVEL_RAW MIPS_ISA_LEVEL_RAW
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#endif /* CONFIG_CPU_MIPSR6 */
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#endif /* _ASM_COMPILER_H */
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