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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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22dd9ae8af
Register range, being subject to register diagnostic, can vary among different NVMs. We will try to identify the full range and use it for a register test. This is needed to avoid false test results. If we fail to define the proper register range we will test only the first register from that group. Change-ID: Ieee7173c719733b61d3733177a94dc557eb7b3fd Signed-off-by: Kamil Krawczyk <kamil.krawczyk@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
155 lines
4.8 KiB
C
155 lines
4.8 KiB
C
/*******************************************************************************
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*
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* Intel Ethernet Controller XL710 Family Linux Driver
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* Copyright(c) 2013 - 2014 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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* Contact Information:
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* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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******************************************************************************/
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#include "i40e_diag.h"
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#include "i40e_prototype.h"
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/**
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* i40e_diag_reg_pattern_test
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* @hw: pointer to the hw struct
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* @reg: reg to be tested
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* @mask: bits to be touched
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**/
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static i40e_status i40e_diag_reg_pattern_test(struct i40e_hw *hw,
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u32 reg, u32 mask)
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{
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const u32 patterns[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
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u32 pat, val, orig_val;
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int i;
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orig_val = rd32(hw, reg);
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for (i = 0; i < ARRAY_SIZE(patterns); i++) {
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pat = patterns[i];
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wr32(hw, reg, (pat & mask));
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val = rd32(hw, reg);
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if ((val & mask) != (pat & mask)) {
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i40e_debug(hw, I40E_DEBUG_DIAG,
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"%s: reg pattern test failed - reg 0x%08x pat 0x%08x val 0x%08x\n",
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__func__, reg, pat, val);
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return I40E_ERR_DIAG_TEST_FAILED;
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}
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}
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wr32(hw, reg, orig_val);
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val = rd32(hw, reg);
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if (val != orig_val) {
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i40e_debug(hw, I40E_DEBUG_DIAG,
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"%s: reg restore test failed - reg 0x%08x orig_val 0x%08x val 0x%08x\n",
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__func__, reg, orig_val, val);
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return I40E_ERR_DIAG_TEST_FAILED;
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}
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return 0;
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}
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struct i40e_diag_reg_test_info i40e_reg_list[] = {
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/* offset mask elements stride */
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{I40E_QTX_CTL(0), 0x0000FFBF, 1,
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I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
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{I40E_PFINT_ITR0(0), 0x00000FFF, 3,
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I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
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{I40E_PFINT_ITRN(0, 0), 0x00000FFF, 1,
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I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
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{I40E_PFINT_ITRN(1, 0), 0x00000FFF, 1,
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I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
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{I40E_PFINT_ITRN(2, 0), 0x00000FFF, 1,
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I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
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{I40E_PFINT_STAT_CTL0, 0x0000000C, 1, 0},
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{I40E_PFINT_LNKLST0, 0x00001FFF, 1, 0},
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{I40E_PFINT_LNKLSTN(0), 0x000007FF, 1,
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I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},
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{I40E_QINT_TQCTL(0), 0x000000FF, 1,
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I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},
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{I40E_QINT_RQCTL(0), 0x000000FF, 1,
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I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},
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{I40E_PFINT_ICR0_ENA, 0xF7F20000, 1, 0},
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{ 0 }
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};
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/**
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* i40e_diag_reg_test
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* @hw: pointer to the hw struct
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*
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* Perform registers diagnostic test
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**/
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i40e_status i40e_diag_reg_test(struct i40e_hw *hw)
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{
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i40e_status ret_code = 0;
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u32 reg, mask;
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u32 i, j;
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for (i = 0; i40e_reg_list[i].offset != 0 &&
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!ret_code; i++) {
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/* set actual reg range for dynamically allocated resources */
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if (i40e_reg_list[i].offset == I40E_QTX_CTL(0) &&
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hw->func_caps.num_tx_qp != 0)
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i40e_reg_list[i].elements = hw->func_caps.num_tx_qp;
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if ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) ||
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i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) ||
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i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) ||
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i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) ||
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i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) &&
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hw->func_caps.num_msix_vectors != 0)
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i40e_reg_list[i].elements =
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hw->func_caps.num_msix_vectors - 1;
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/* test register access */
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mask = i40e_reg_list[i].mask;
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for (j = 0; j < i40e_reg_list[i].elements && !ret_code; j++) {
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reg = i40e_reg_list[i].offset +
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(j * i40e_reg_list[i].stride);
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ret_code = i40e_diag_reg_pattern_test(hw, reg, mask);
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}
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}
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return ret_code;
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}
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/**
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* i40e_diag_eeprom_test
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* @hw: pointer to the hw struct
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*
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* Perform EEPROM diagnostic test
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**/
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i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw)
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{
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i40e_status ret_code;
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u16 reg_val;
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/* read NVM control word and if NVM valid, validate EEPROM checksum*/
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ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, ®_val);
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if (!ret_code &&
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((reg_val & I40E_SR_CONTROL_WORD_1_MASK) ==
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(0x01 << I40E_SR_CONTROL_WORD_1_SHIFT))) {
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ret_code = i40e_validate_nvm_checksum(hw, NULL);
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} else {
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ret_code = I40E_ERR_DIAG_TEST_FAILED;
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}
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return ret_code;
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}
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