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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
590 lines
18 KiB
C
590 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) ST-Ericsson SA 2012
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*
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* Author: Ola Lilja <ola.o.lilja@stericsson.com>,
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* Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
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* Roger Nilsson <roger.xr.nilsson@stericsson.com>,
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* for ST-Ericsson.
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*
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* Based on the early work done by:
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* Mikko J. Lehto <mikko.lehto@symbio.com>,
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* Mikko Sarmanne <mikko.sarmanne@symbio.com>,
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* for ST-Ericsson.
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*
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* License terms:
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*/
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#ifndef AB8500_CODEC_REGISTERS_H
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#define AB8500_CODEC_REGISTERS_H
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#define AB8500_SUPPORTED_RATE (SNDRV_PCM_RATE_48000)
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#define AB8500_SUPPORTED_FMT (SNDRV_PCM_FMTBIT_S16_LE)
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/* AB8500 interface slot offset definitions */
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#define AB8500_AD_DATA0_OFFSET 0
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#define AB8500_DA_DATA0_OFFSET 8
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#define AB8500_AD_DATA1_OFFSET 16
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#define AB8500_DA_DATA1_OFFSET 24
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/* AB8500 audio bank (0x0d) register definitions */
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#define AB8500_POWERUP 0x00
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#define AB8500_AUDSWRESET 0x01
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#define AB8500_ADPATHENA 0x02
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#define AB8500_DAPATHENA 0x03
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#define AB8500_ANACONF1 0x04
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#define AB8500_ANACONF2 0x05
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#define AB8500_DIGMICCONF 0x06
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#define AB8500_ANACONF3 0x07
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#define AB8500_ANACONF4 0x08
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#define AB8500_DAPATHCONF 0x09
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#define AB8500_MUTECONF 0x0A
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#define AB8500_SHORTCIRCONF 0x0B
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#define AB8500_ANACONF5 0x0C
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#define AB8500_ENVCPCONF 0x0D
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#define AB8500_SIGENVCONF 0x0E
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#define AB8500_PWMGENCONF1 0x0F
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#define AB8500_PWMGENCONF2 0x10
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#define AB8500_PWMGENCONF3 0x11
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#define AB8500_PWMGENCONF4 0x12
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#define AB8500_PWMGENCONF5 0x13
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#define AB8500_ANAGAIN1 0x14
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#define AB8500_ANAGAIN2 0x15
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#define AB8500_ANAGAIN3 0x16
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#define AB8500_ANAGAIN4 0x17
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#define AB8500_DIGLINHSLGAIN 0x18
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#define AB8500_DIGLINHSRGAIN 0x19
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#define AB8500_ADFILTCONF 0x1A
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#define AB8500_DIGIFCONF1 0x1B
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#define AB8500_DIGIFCONF2 0x1C
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#define AB8500_DIGIFCONF3 0x1D
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#define AB8500_DIGIFCONF4 0x1E
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#define AB8500_ADSLOTSEL1 0x1F
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#define AB8500_ADSLOTSEL2 0x20
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#define AB8500_ADSLOTSEL3 0x21
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#define AB8500_ADSLOTSEL4 0x22
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#define AB8500_ADSLOTSEL5 0x23
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#define AB8500_ADSLOTSEL6 0x24
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#define AB8500_ADSLOTSEL7 0x25
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#define AB8500_ADSLOTSEL8 0x26
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#define AB8500_ADSLOTSEL9 0x27
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#define AB8500_ADSLOTSEL10 0x28
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#define AB8500_ADSLOTSEL11 0x29
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#define AB8500_ADSLOTSEL12 0x2A
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#define AB8500_ADSLOTSEL13 0x2B
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#define AB8500_ADSLOTSEL14 0x2C
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#define AB8500_ADSLOTSEL15 0x2D
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#define AB8500_ADSLOTSEL16 0x2E
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#define AB8500_ADSLOTSEL(slot) (AB8500_ADSLOTSEL1 + (slot >> 1))
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#define AB8500_ADSLOTHIZCTRL1 0x2F
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#define AB8500_ADSLOTHIZCTRL2 0x30
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#define AB8500_ADSLOTHIZCTRL3 0x31
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#define AB8500_ADSLOTHIZCTRL4 0x32
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#define AB8500_DASLOTCONF1 0x33
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#define AB8500_DASLOTCONF2 0x34
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#define AB8500_DASLOTCONF3 0x35
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#define AB8500_DASLOTCONF4 0x36
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#define AB8500_DASLOTCONF5 0x37
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#define AB8500_DASLOTCONF6 0x38
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#define AB8500_DASLOTCONF7 0x39
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#define AB8500_DASLOTCONF8 0x3A
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#define AB8500_CLASSDCONF1 0x3B
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#define AB8500_CLASSDCONF2 0x3C
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#define AB8500_CLASSDCONF3 0x3D
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#define AB8500_DMICFILTCONF 0x3E
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#define AB8500_DIGMULTCONF1 0x3F
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#define AB8500_DIGMULTCONF2 0x40
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#define AB8500_ADDIGGAIN1 0x41
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#define AB8500_ADDIGGAIN2 0x42
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#define AB8500_ADDIGGAIN3 0x43
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#define AB8500_ADDIGGAIN4 0x44
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#define AB8500_ADDIGGAIN5 0x45
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#define AB8500_ADDIGGAIN6 0x46
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#define AB8500_DADIGGAIN1 0x47
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#define AB8500_DADIGGAIN2 0x48
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#define AB8500_DADIGGAIN3 0x49
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#define AB8500_DADIGGAIN4 0x4A
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#define AB8500_DADIGGAIN5 0x4B
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#define AB8500_DADIGGAIN6 0x4C
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#define AB8500_ADDIGLOOPGAIN1 0x4D
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#define AB8500_ADDIGLOOPGAIN2 0x4E
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#define AB8500_HSLEARDIGGAIN 0x4F
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#define AB8500_HSRDIGGAIN 0x50
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#define AB8500_SIDFIRGAIN1 0x51
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#define AB8500_SIDFIRGAIN2 0x52
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#define AB8500_ANCCONF1 0x53
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#define AB8500_ANCCONF2 0x54
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#define AB8500_ANCCONF3 0x55
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#define AB8500_ANCCONF4 0x56
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#define AB8500_ANCCONF5 0x57
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#define AB8500_ANCCONF6 0x58
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#define AB8500_ANCCONF7 0x59
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#define AB8500_ANCCONF8 0x5A
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#define AB8500_ANCCONF9 0x5B
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#define AB8500_ANCCONF10 0x5C
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#define AB8500_ANCCONF11 0x5D
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#define AB8500_ANCCONF12 0x5E
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#define AB8500_ANCCONF13 0x5F
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#define AB8500_ANCCONF14 0x60
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#define AB8500_SIDFIRADR 0x61
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#define AB8500_SIDFIRCOEF1 0x62
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#define AB8500_SIDFIRCOEF2 0x63
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#define AB8500_SIDFIRCONF 0x64
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#define AB8500_AUDINTMASK1 0x65
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#define AB8500_AUDINTSOURCE1 0x66
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#define AB8500_AUDINTMASK2 0x67
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#define AB8500_AUDINTSOURCE2 0x68
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#define AB8500_FIFOCONF1 0x69
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#define AB8500_FIFOCONF2 0x6A
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#define AB8500_FIFOCONF3 0x6B
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#define AB8500_FIFOCONF4 0x6C
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#define AB8500_FIFOCONF5 0x6D
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#define AB8500_FIFOCONF6 0x6E
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#define AB8500_AUDREV 0x6F
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#define AB8500_FIRST_REG AB8500_POWERUP
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#define AB8500_LAST_REG AB8500_AUDREV
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#define AB8500_CACHEREGNUM (AB8500_LAST_REG + 1)
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#define AB8500_MASK_ALL 0xFF
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#define AB8500_MASK_SLOT(slot) ((slot & 1) ? 0xF0 : 0x0F)
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#define AB8500_MASK_NONE 0x00
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/* AB8500_POWERUP */
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#define AB8500_POWERUP_POWERUP 7
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#define AB8500_POWERUP_ENANA 3
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/* AB8500_AUDSWRESET */
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#define AB8500_AUDSWRESET_SWRESET 7
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/* AB8500_ADPATHENA */
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#define AB8500_ADPATHENA_ENAD12 7
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#define AB8500_ADPATHENA_ENAD34 5
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#define AB8500_ADPATHENA_ENAD5768 3
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/* AB8500_DAPATHENA */
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#define AB8500_DAPATHENA_ENDA1 7
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#define AB8500_DAPATHENA_ENDA2 6
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#define AB8500_DAPATHENA_ENDA3 5
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#define AB8500_DAPATHENA_ENDA4 4
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#define AB8500_DAPATHENA_ENDA5 3
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#define AB8500_DAPATHENA_ENDA6 2
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/* AB8500_ANACONF1 */
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#define AB8500_ANACONF1_HSLOWPOW 7
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#define AB8500_ANACONF1_DACLOWPOW1 6
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#define AB8500_ANACONF1_DACLOWPOW0 5
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#define AB8500_ANACONF1_EARDACLOWPOW 4
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#define AB8500_ANACONF1_EARSELCM 2
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#define AB8500_ANACONF1_HSHPEN 1
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#define AB8500_ANACONF1_EARDRVLOWPOW 0
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/* AB8500_ANACONF2 */
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#define AB8500_ANACONF2_ENMIC1 7
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#define AB8500_ANACONF2_ENMIC2 6
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#define AB8500_ANACONF2_ENLINL 5
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#define AB8500_ANACONF2_ENLINR 4
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#define AB8500_ANACONF2_MUTMIC1 3
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#define AB8500_ANACONF2_MUTMIC2 2
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#define AB8500_ANACONF2_MUTLINL 1
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#define AB8500_ANACONF2_MUTLINR 0
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/* AB8500_DIGMICCONF */
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#define AB8500_DIGMICCONF_ENDMIC1 7
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#define AB8500_DIGMICCONF_ENDMIC2 6
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#define AB8500_DIGMICCONF_ENDMIC3 5
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#define AB8500_DIGMICCONF_ENDMIC4 4
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#define AB8500_DIGMICCONF_ENDMIC5 3
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#define AB8500_DIGMICCONF_ENDMIC6 2
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#define AB8500_DIGMICCONF_HSFADSPEED 0
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/* AB8500_ANACONF3 */
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#define AB8500_ANACONF3_MIC1SEL 7
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#define AB8500_ANACONF3_LINRSEL 6
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#define AB8500_ANACONF3_ENDRVHSL 5
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#define AB8500_ANACONF3_ENDRVHSR 4
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#define AB8500_ANACONF3_ENADCMIC 2
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#define AB8500_ANACONF3_ENADCLINL 1
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#define AB8500_ANACONF3_ENADCLINR 0
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/* AB8500_ANACONF4 */
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#define AB8500_ANACONF4_DISPDVSS 7
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#define AB8500_ANACONF4_ENEAR 6
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#define AB8500_ANACONF4_ENHSL 5
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#define AB8500_ANACONF4_ENHSR 4
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#define AB8500_ANACONF4_ENHFL 3
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#define AB8500_ANACONF4_ENHFR 2
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#define AB8500_ANACONF4_ENVIB1 1
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#define AB8500_ANACONF4_ENVIB2 0
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/* AB8500_DAPATHCONF */
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#define AB8500_DAPATHCONF_ENDACEAR 6
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#define AB8500_DAPATHCONF_ENDACHSL 5
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#define AB8500_DAPATHCONF_ENDACHSR 4
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#define AB8500_DAPATHCONF_ENDACHFL 3
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#define AB8500_DAPATHCONF_ENDACHFR 2
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#define AB8500_DAPATHCONF_ENDACVIB1 1
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#define AB8500_DAPATHCONF_ENDACVIB2 0
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/* AB8500_MUTECONF */
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#define AB8500_MUTECONF_MUTEAR 6
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#define AB8500_MUTECONF_MUTHSL 5
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#define AB8500_MUTECONF_MUTHSR 4
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#define AB8500_MUTECONF_MUTDACEAR 2
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#define AB8500_MUTECONF_MUTDACHSL 1
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#define AB8500_MUTECONF_MUTDACHSR 0
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/* AB8500_SHORTCIRCONF */
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#define AB8500_SHORTCIRCONF_ENSHORTPWD 7
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#define AB8500_SHORTCIRCONF_EARSHORTDIS 6
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#define AB8500_SHORTCIRCONF_HSSHORTDIS 5
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#define AB8500_SHORTCIRCONF_HSPULLDEN 4
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#define AB8500_SHORTCIRCONF_HSOSCEN 2
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#define AB8500_SHORTCIRCONF_HSFADDIS 1
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#define AB8500_SHORTCIRCONF_HSZCDDIS 0
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/* Zero cross should be disabled */
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/* AB8500_ANACONF5 */
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#define AB8500_ANACONF5_ENCPHS 7
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#define AB8500_ANACONF5_HSLDACTOLOL 5
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#define AB8500_ANACONF5_HSRDACTOLOR 4
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#define AB8500_ANACONF5_ENLOL 3
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#define AB8500_ANACONF5_ENLOR 2
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#define AB8500_ANACONF5_HSAUTOEN 0
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/* AB8500_ENVCPCONF */
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#define AB8500_ENVCPCONF_ENVDETHTHRE 4
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#define AB8500_ENVCPCONF_ENVDETLTHRE 0
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#define AB8500_ENVCPCONF_ENVDETHTHRE_MAX 0x0F
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#define AB8500_ENVCPCONF_ENVDETLTHRE_MAX 0x0F
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/* AB8500_SIGENVCONF */
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#define AB8500_SIGENVCONF_CPLVEN 5
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#define AB8500_SIGENVCONF_ENVDETCPEN 4
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#define AB8500_SIGENVCONF_ENVDETTIME 0
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#define AB8500_SIGENVCONF_ENVDETTIME_MAX 0x0F
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/* AB8500_PWMGENCONF1 */
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#define AB8500_PWMGENCONF1_PWMTOVIB1 7
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#define AB8500_PWMGENCONF1_PWMTOVIB2 6
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#define AB8500_PWMGENCONF1_PWM1CTRL 5
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#define AB8500_PWMGENCONF1_PWM2CTRL 4
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#define AB8500_PWMGENCONF1_PWM1NCTRL 3
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#define AB8500_PWMGENCONF1_PWM1PCTRL 2
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#define AB8500_PWMGENCONF1_PWM2NCTRL 1
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#define AB8500_PWMGENCONF1_PWM2PCTRL 0
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/* AB8500_PWMGENCONF2 */
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/* AB8500_PWMGENCONF3 */
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/* AB8500_PWMGENCONF4 */
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/* AB8500_PWMGENCONF5 */
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#define AB8500_PWMGENCONFX_PWMVIBXPOL 7
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#define AB8500_PWMGENCONFX_PWMVIBXDUTCYC 0
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#define AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX 0x64
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/* AB8500_ANAGAIN1 */
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/* AB8500_ANAGAIN2 */
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#define AB8500_ANAGAINX_ENSEMICX 7
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#define AB8500_ANAGAINX_LOWPOWMICX 6
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#define AB8500_ANAGAINX_MICXGAIN 0
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#define AB8500_ANAGAINX_MICXGAIN_MAX 0x1F
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/* AB8500_ANAGAIN3 */
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#define AB8500_ANAGAIN3_HSLGAIN 4
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#define AB8500_ANAGAIN3_HSRGAIN 0
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#define AB8500_ANAGAIN3_HSXGAIN_MAX 0x0F
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/* AB8500_ANAGAIN4 */
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#define AB8500_ANAGAIN4_LINLGAIN 4
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#define AB8500_ANAGAIN4_LINRGAIN 0
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#define AB8500_ANAGAIN4_LINXGAIN_MAX 0x0F
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/* AB8500_DIGLINHSLGAIN */
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/* AB8500_DIGLINHSRGAIN */
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#define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN 0
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#define AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX 0x13
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/* AB8500_ADFILTCONF */
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#define AB8500_ADFILTCONF_AD1NH 7
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#define AB8500_ADFILTCONF_AD2NH 6
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#define AB8500_ADFILTCONF_AD3NH 5
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#define AB8500_ADFILTCONF_AD4NH 4
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#define AB8500_ADFILTCONF_AD1VOICE 3
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#define AB8500_ADFILTCONF_AD2VOICE 2
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#define AB8500_ADFILTCONF_AD3VOICE 1
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#define AB8500_ADFILTCONF_AD4VOICE 0
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/* AB8500_DIGIFCONF1 */
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#define AB8500_DIGIFCONF1_ENMASTGEN 7
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#define AB8500_DIGIFCONF1_IF1BITCLKOS1 6
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#define AB8500_DIGIFCONF1_IF1BITCLKOS0 5
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#define AB8500_DIGIFCONF1_ENFSBITCLK1 4
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#define AB8500_DIGIFCONF1_IF0BITCLKOS1 2
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#define AB8500_DIGIFCONF1_IF0BITCLKOS0 1
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#define AB8500_DIGIFCONF1_ENFSBITCLK0 0
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/* AB8500_DIGIFCONF2 */
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#define AB8500_DIGIFCONF2_FSYNC0P 6
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#define AB8500_DIGIFCONF2_BITCLK0P 5
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#define AB8500_DIGIFCONF2_IF0DEL 4
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#define AB8500_DIGIFCONF2_IF0FORMAT1 3
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#define AB8500_DIGIFCONF2_IF0FORMAT0 2
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#define AB8500_DIGIFCONF2_IF0WL1 1
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#define AB8500_DIGIFCONF2_IF0WL0 0
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/* AB8500_DIGIFCONF3 */
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#define AB8500_DIGIFCONF3_IF0DATOIF1AD 7
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#define AB8500_DIGIFCONF3_IF0CLKTOIF1CLK 6
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#define AB8500_DIGIFCONF3_IF1MASTER 5
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#define AB8500_DIGIFCONF3_IF1DATOIF0AD 3
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#define AB8500_DIGIFCONF3_IF1CLKTOIF0CLK 2
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#define AB8500_DIGIFCONF3_IF0MASTER 1
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#define AB8500_DIGIFCONF3_IF0BFIFOEN 0
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/* AB8500_DIGIFCONF4 */
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#define AB8500_DIGIFCONF4_FSYNC1P 6
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#define AB8500_DIGIFCONF4_BITCLK1P 5
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#define AB8500_DIGIFCONF4_IF1DEL 4
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#define AB8500_DIGIFCONF4_IF1FORMAT1 3
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#define AB8500_DIGIFCONF4_IF1FORMAT0 2
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#define AB8500_DIGIFCONF4_IF1WL1 1
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#define AB8500_DIGIFCONF4_IF1WL0 0
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/* AB8500_ADSLOTSELX */
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#define AB8500_AD_OUT1 0x0
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#define AB8500_AD_OUT2 0x1
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#define AB8500_AD_OUT3 0x2
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#define AB8500_AD_OUT4 0x3
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#define AB8500_AD_OUT5 0x4
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#define AB8500_AD_OUT6 0x5
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#define AB8500_AD_OUT7 0x6
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#define AB8500_AD_OUT8 0x7
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#define AB8500_ZEROES 0x8
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#define AB8500_TRISTATE 0xF
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#define AB8500_ADSLOTSELX_EVEN_SHIFT 0
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#define AB8500_ADSLOTSELX_ODD_SHIFT 4
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#define AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(out, slot) \
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((out) << (((slot) & 1) ? \
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AB8500_ADSLOTSELX_ODD_SHIFT : AB8500_ADSLOTSELX_EVEN_SHIFT))
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/* AB8500_ADSLOTHIZCTRL1 */
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/* AB8500_ADSLOTHIZCTRL2 */
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/* AB8500_ADSLOTHIZCTRL3 */
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/* AB8500_ADSLOTHIZCTRL4 */
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/* AB8500_DASLOTCONF1 */
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#define AB8500_DASLOTCONF1_DA12VOICE 7
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#define AB8500_DASLOTCONF1_SWAPDA12_34 6
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#define AB8500_DASLOTCONF1_DAI7TOADO1 5
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/* AB8500_DASLOTCONF2 */
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#define AB8500_DASLOTCONF2_DAI8TOADO2 5
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/* AB8500_DASLOTCONF3 */
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#define AB8500_DASLOTCONF3_DA34VOICE 7
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#define AB8500_DASLOTCONF3_DAI7TOADO3 5
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/* AB8500_DASLOTCONF4 */
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#define AB8500_DASLOTCONF4_DAI8TOADO4 5
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/* AB8500_DASLOTCONF5 */
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#define AB8500_DASLOTCONF5_DA56VOICE 7
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#define AB8500_DASLOTCONF5_DAI7TOADO5 5
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/* AB8500_DASLOTCONF6 */
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#define AB8500_DASLOTCONF6_DAI8TOADO6 5
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/* AB8500_DASLOTCONF7 */
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#define AB8500_DASLOTCONF7_DAI8TOADO7 5
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/* AB8500_DASLOTCONF8 */
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#define AB8500_DASLOTCONF8_DAI7TOADO8 5
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#define AB8500_DASLOTCONFX_SLTODAX_SHIFT 0
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#define AB8500_DASLOTCONFX_SLTODAX_MASK 0x1F
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/* AB8500_CLASSDCONF1 */
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#define AB8500_CLASSDCONF1_PARLHF 7
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#define AB8500_CLASSDCONF1_PARLVIB 6
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#define AB8500_CLASSDCONF1_VIB1SWAPEN 3
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#define AB8500_CLASSDCONF1_VIB2SWAPEN 2
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#define AB8500_CLASSDCONF1_HFLSWAPEN 1
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#define AB8500_CLASSDCONF1_HFRSWAPEN 0
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/* AB8500_CLASSDCONF2 */
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#define AB8500_CLASSDCONF2_FIRBYP3 7
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#define AB8500_CLASSDCONF2_FIRBYP2 6
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#define AB8500_CLASSDCONF2_FIRBYP1 5
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#define AB8500_CLASSDCONF2_FIRBYP0 4
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#define AB8500_CLASSDCONF2_HIGHVOLEN3 3
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#define AB8500_CLASSDCONF2_HIGHVOLEN2 2
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#define AB8500_CLASSDCONF2_HIGHVOLEN1 1
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#define AB8500_CLASSDCONF2_HIGHVOLEN0 0
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/* AB8500_CLASSDCONF3 */
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#define AB8500_CLASSDCONF3_DITHHPGAIN 4
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#define AB8500_CLASSDCONF3_DITHHPGAIN_MAX 0x0A
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#define AB8500_CLASSDCONF3_DITHWGAIN 0
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#define AB8500_CLASSDCONF3_DITHWGAIN_MAX 0x0A
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/* AB8500_DMICFILTCONF */
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#define AB8500_DMICFILTCONF_ANCINSEL 7
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#define AB8500_DMICFILTCONF_DA3TOEAR 6
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#define AB8500_DMICFILTCONF_DMIC1SINC3 5
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#define AB8500_DMICFILTCONF_DMIC2SINC3 4
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#define AB8500_DMICFILTCONF_DMIC3SINC3 3
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#define AB8500_DMICFILTCONF_DMIC4SINC3 2
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#define AB8500_DMICFILTCONF_DMIC5SINC3 1
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#define AB8500_DMICFILTCONF_DMIC6SINC3 0
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/* AB8500_DIGMULTCONF1 */
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#define AB8500_DIGMULTCONF1_DATOHSLEN 7
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#define AB8500_DIGMULTCONF1_DATOHSREN 6
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#define AB8500_DIGMULTCONF1_AD1SEL 5
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#define AB8500_DIGMULTCONF1_AD2SEL 4
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#define AB8500_DIGMULTCONF1_AD3SEL 3
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#define AB8500_DIGMULTCONF1_AD5SEL 2
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#define AB8500_DIGMULTCONF1_AD6SEL 1
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#define AB8500_DIGMULTCONF1_ANCSEL 0
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/* AB8500_DIGMULTCONF2 */
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#define AB8500_DIGMULTCONF2_DATOHFREN 7
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#define AB8500_DIGMULTCONF2_DATOHFLEN 6
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#define AB8500_DIGMULTCONF2_HFRSEL 5
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#define AB8500_DIGMULTCONF2_HFLSEL 4
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#define AB8500_DIGMULTCONF2_FIRSID1SEL 2
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#define AB8500_DIGMULTCONF2_FIRSID2SEL 0
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/* AB8500_ADDIGGAIN1 */
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/* AB8500_ADDIGGAIN2 */
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/* AB8500_ADDIGGAIN3 */
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/* AB8500_ADDIGGAIN4 */
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/* AB8500_ADDIGGAIN5 */
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/* AB8500_ADDIGGAIN6 */
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#define AB8500_ADDIGGAINX_FADEDISADX 6
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#define AB8500_ADDIGGAINX_ADXGAIN_MAX 0x3F
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/* AB8500_DADIGGAIN1 */
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/* AB8500_DADIGGAIN2 */
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/* AB8500_DADIGGAIN3 */
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/* AB8500_DADIGGAIN4 */
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/* AB8500_DADIGGAIN5 */
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/* AB8500_DADIGGAIN6 */
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#define AB8500_DADIGGAINX_FADEDISDAX 6
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#define AB8500_DADIGGAINX_DAXGAIN_MAX 0x3F
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/* AB8500_ADDIGLOOPGAIN1 */
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/* AB8500_ADDIGLOOPGAIN2 */
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#define AB8500_ADDIGLOOPGAINX_FADEDISADXL 6
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#define AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX 0x3F
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/* AB8500_HSLEARDIGGAIN */
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#define AB8500_HSLEARDIGGAIN_HSSINC1 7
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#define AB8500_HSLEARDIGGAIN_FADEDISHSL 4
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#define AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX 0x09
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/* AB8500_HSRDIGGAIN */
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#define AB8500_HSRDIGGAIN_FADESPEED 6
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#define AB8500_HSRDIGGAIN_FADEDISHSR 4
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#define AB8500_HSRDIGGAIN_HSRDGAIN_MAX 0x09
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/* AB8500_SIDFIRGAIN1 */
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/* AB8500_SIDFIRGAIN2 */
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#define AB8500_SIDFIRGAINX_FIRSIDXGAIN_MAX 0x1F
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/* AB8500_ANCCONF1 */
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#define AB8500_ANCCONF1_ANCIIRUPDATE 3
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#define AB8500_ANCCONF1_ENANC 2
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#define AB8500_ANCCONF1_ANCIIRINIT 1
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#define AB8500_ANCCONF1_ANCFIRUPDATE 0
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/* AB8500_ANCCONF2 */
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#define AB8500_ANCCONF2_SHIFT 5
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#define AB8500_ANCCONF2_MIN -0x10
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#define AB8500_ANCCONF2_MAX 0xF
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/* AB8500_ANCCONF3 */
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#define AB8500_ANCCONF3_SHIFT 5
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#define AB8500_ANCCONF3_MIN -0x10
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#define AB8500_ANCCONF3_MAX 0xF
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/* AB8500_ANCCONF4 */
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#define AB8500_ANCCONF4_SHIFT 5
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#define AB8500_ANCCONF4_MIN -0x10
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#define AB8500_ANCCONF4_MAX 0xF
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/* AB8500_ANC_FIR_COEFFS */
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#define AB8500_ANC_FIR_COEFF_MIN -0x8000
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#define AB8500_ANC_FIR_COEFF_MAX 0x7FFF
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#define AB8500_ANC_FIR_COEFFS 15
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/* AB8500_ANC_IIR_COEFFS */
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#define AB8500_ANC_IIR_COEFF_MIN -0x800000
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#define AB8500_ANC_IIR_COEFF_MAX 0x7FFFFF
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#define AB8500_ANC_IIR_COEFFS 24
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/* AB8500_ANC_WARP_DELAY */
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#define AB8500_ANC_WARP_DELAY_SHIFT 16
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#define AB8500_ANC_WARP_DELAY_MIN 0x0000
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#define AB8500_ANC_WARP_DELAY_MAX 0xFFFF
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/* AB8500_ANCCONF11 */
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/* AB8500_ANCCONF12 */
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/* AB8500_ANCCONF13 */
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/* AB8500_ANCCONF14 */
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/* AB8500_SIDFIRADR */
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#define AB8500_SIDFIRADR_FIRSIDSET 7
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#define AB8500_SIDFIRADR_ADDRESS_SHIFT 0
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#define AB8500_SIDFIRADR_ADDRESS_MAX 0x7F
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/* AB8500_SIDFIRCOEF1 */
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/* AB8500_SIDFIRCOEF2 */
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#define AB8500_SID_FIR_COEFF_MIN 0
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#define AB8500_SID_FIR_COEFF_MAX 0xFFFF
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#define AB8500_SID_FIR_COEFFS 128
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/* AB8500_SIDFIRCONF */
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#define AB8500_SIDFIRCONF_ENFIRSIDS 2
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#define AB8500_SIDFIRCONF_FIRSIDSTOIF1 1
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#define AB8500_SIDFIRCONF_FIRSIDBUSY 0
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/* AB8500_AUDINTMASK1 */
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/* AB8500_AUDINTSOURCE1 */
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/* AB8500_AUDINTMASK2 */
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/* AB8500_AUDINTSOURCE2 */
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/* AB8500_FIFOCONF1 */
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#define AB8500_FIFOCONF1_BFIFOMASK 0x80
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#define AB8500_FIFOCONF1_BFIFO19M2 0x40
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#define AB8500_FIFOCONF1_BFIFOINT_SHIFT 0
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#define AB8500_FIFOCONF1_BFIFOINT_MAX 0x3F
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/* AB8500_FIFOCONF2 */
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#define AB8500_FIFOCONF2_BFIFOTX_SHIFT 0
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#define AB8500_FIFOCONF2_BFIFOTX_MAX 0xFF
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/* AB8500_FIFOCONF3 */
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#define AB8500_FIFOCONF3_BFIFOEXSL_SHIFT 5
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#define AB8500_FIFOCONF3_BFIFOEXSL_MAX 0x5
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#define AB8500_FIFOCONF3_PREBITCLK0_SHIFT 2
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#define AB8500_FIFOCONF3_PREBITCLK0_MAX 0x7
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#define AB8500_FIFOCONF3_BFIFOMAST_SHIFT 1
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#define AB8500_FIFOCONF3_BFIFORUN_SHIFT 0
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/* AB8500_FIFOCONF4 */
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#define AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT 0
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#define AB8500_FIFOCONF4_BFIFOFRAMSW_MAX 0xFF
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/* AB8500_FIFOCONF5 */
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#define AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT 0
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#define AB8500_FIFOCONF5_BFIFOWAKEUP_MAX 0xFF
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/* AB8500_FIFOCONF6 */
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#define AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT 0
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#define AB8500_FIFOCONF6_BFIFOSAMPLE_MAX 0xFF
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/* AB8500_AUDREV */
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#endif
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