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c6345ab1a3
In order to safely work around anomaly 05000491, we have to execute IFLUSH from L1 instruction sram. The trouble with multi-core systems is that all L1 sram is visible only to the active core. So we can't just place the functions into L1 and call it directly. We need to setup a jump table and place the entry point in external memory. This will call the right func based on the active core. In the process, convert from the manual relocation of a small bit of code into Core B's L1 to the more general framework we already have in place for loading arbitrary pieces of code into L1. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> |
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| .. | ||
| arch_checks.c | ||
| cache-c.c | ||
| cache.S | ||
| clocks-init.c | ||
| cpufreq.c | ||
| dpmc_modes.S | ||
| dpmc.c | ||
| entry.S | ||
| head.S | ||
| interrupt.S | ||
| ints-priority.c | ||
| Makefile | ||
| pm.c | ||
| smp.c | ||