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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a910f251ee
On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks (modelled as NKMP with no K) and have fixed post-dividers. Add fixed post divider support to the NKMP style clocks. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
215 lines
5.4 KiB
C
215 lines
5.4 KiB
C
/*
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* Copyright (C) 2016 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include "ccu_gate.h"
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#include "ccu_nkmp.h"
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struct _ccu_nkmp {
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unsigned long n, min_n, max_n;
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unsigned long k, min_k, max_k;
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unsigned long m, min_m, max_m;
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unsigned long p, min_p, max_p;
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};
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static unsigned long ccu_nkmp_calc_rate(unsigned long parent,
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unsigned long n, unsigned long k,
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unsigned long m, unsigned long p)
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{
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u64 rate = parent;
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rate *= n * k;
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do_div(rate, m * p);
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return rate;
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}
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static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
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struct _ccu_nkmp *nkmp)
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{
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unsigned long best_rate = 0;
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unsigned long best_n = 0, best_k = 0, best_m = 0, best_p = 0;
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unsigned long _n, _k, _m, _p;
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for (_k = nkmp->min_k; _k <= nkmp->max_k; _k++) {
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for (_n = nkmp->min_n; _n <= nkmp->max_n; _n++) {
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for (_m = nkmp->min_m; _m <= nkmp->max_m; _m++) {
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for (_p = nkmp->min_p; _p <= nkmp->max_p; _p <<= 1) {
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unsigned long tmp_rate;
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tmp_rate = ccu_nkmp_calc_rate(parent,
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_n, _k,
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_m, _p);
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if (tmp_rate > rate)
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continue;
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if ((rate - tmp_rate) < (rate - best_rate)) {
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best_rate = tmp_rate;
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best_n = _n;
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best_k = _k;
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best_m = _m;
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best_p = _p;
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}
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}
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}
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}
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}
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nkmp->n = best_n;
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nkmp->k = best_k;
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nkmp->m = best_m;
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nkmp->p = best_p;
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}
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static void ccu_nkmp_disable(struct clk_hw *hw)
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{
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struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
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return ccu_gate_helper_disable(&nkmp->common, nkmp->enable);
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}
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static int ccu_nkmp_enable(struct clk_hw *hw)
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{
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struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
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return ccu_gate_helper_enable(&nkmp->common, nkmp->enable);
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}
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static int ccu_nkmp_is_enabled(struct clk_hw *hw)
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{
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struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
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return ccu_gate_helper_is_enabled(&nkmp->common, nkmp->enable);
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}
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static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
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unsigned long n, m, k, p, rate;
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u32 reg;
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reg = readl(nkmp->common.base + nkmp->common.reg);
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n = reg >> nkmp->n.shift;
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n &= (1 << nkmp->n.width) - 1;
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n += nkmp->n.offset;
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if (!n)
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n++;
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k = reg >> nkmp->k.shift;
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k &= (1 << nkmp->k.width) - 1;
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k += nkmp->k.offset;
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if (!k)
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k++;
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m = reg >> nkmp->m.shift;
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m &= (1 << nkmp->m.width) - 1;
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m += nkmp->m.offset;
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if (!m)
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m++;
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p = reg >> nkmp->p.shift;
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p &= (1 << nkmp->p.width) - 1;
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rate = ccu_nkmp_calc_rate(parent_rate, n, k, m, 1 << p);
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if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate /= nkmp->fixed_post_div;
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return rate;
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}
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static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
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struct _ccu_nkmp _nkmp;
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if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate *= nkmp->fixed_post_div;
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_nkmp.min_n = nkmp->n.min ?: 1;
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_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
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_nkmp.min_k = nkmp->k.min ?: 1;
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_nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width;
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_nkmp.min_m = 1;
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_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
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_nkmp.min_p = 1;
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_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
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ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
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rate = ccu_nkmp_calc_rate(*parent_rate, _nkmp.n, _nkmp.k,
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_nkmp.m, _nkmp.p);
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if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate = rate / nkmp->fixed_post_div;
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return rate;
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}
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static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
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u32 n_mask, k_mask, m_mask, p_mask;
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struct _ccu_nkmp _nkmp;
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unsigned long flags;
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u32 reg;
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if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate = rate * nkmp->fixed_post_div;
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_nkmp.min_n = nkmp->n.min ?: 1;
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_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
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_nkmp.min_k = nkmp->k.min ?: 1;
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_nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width;
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_nkmp.min_m = 1;
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_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
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_nkmp.min_p = 1;
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_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
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ccu_nkmp_find_best(parent_rate, rate, &_nkmp);
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n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1, nkmp->n.shift);
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k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1, nkmp->k.shift);
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m_mask = GENMASK(nkmp->m.width + nkmp->m.shift - 1, nkmp->m.shift);
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p_mask = GENMASK(nkmp->p.width + nkmp->p.shift - 1, nkmp->p.shift);
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spin_lock_irqsave(nkmp->common.lock, flags);
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reg = readl(nkmp->common.base + nkmp->common.reg);
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reg &= ~(n_mask | k_mask | m_mask | p_mask);
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reg |= ((_nkmp.n - nkmp->n.offset) << nkmp->n.shift) & n_mask;
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reg |= ((_nkmp.k - nkmp->k.offset) << nkmp->k.shift) & k_mask;
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reg |= ((_nkmp.m - nkmp->m.offset) << nkmp->m.shift) & m_mask;
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reg |= (ilog2(_nkmp.p) << nkmp->p.shift) & p_mask;
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writel(reg, nkmp->common.base + nkmp->common.reg);
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spin_unlock_irqrestore(nkmp->common.lock, flags);
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ccu_helper_wait_for_lock(&nkmp->common, nkmp->lock);
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return 0;
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}
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const struct clk_ops ccu_nkmp_ops = {
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.disable = ccu_nkmp_disable,
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.enable = ccu_nkmp_enable,
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.is_enabled = ccu_nkmp_is_enabled,
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.recalc_rate = ccu_nkmp_recalc_rate,
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.round_rate = ccu_nkmp_round_rate,
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.set_rate = ccu_nkmp_set_rate,
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};
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