mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 17:36:25 +07:00
049331f277
The FSGSBASE series turned out to have serious bugs and there is still an open issue which is not fully understood yet. The confidence in those changes has become close to zero especially as the test cases which have been shipped with that series were obviously never run before sending the final series out to LKML. ./fsgsbase_64 >/dev/null Segmentation fault As the merge window is close, the only sane decision is to revert FSGSBASE support. The revert is necessary as this branch has been merged into perf/core already and rebasing all of that a few days before the merge window is not the most brilliant idea. I could definitely slap myself for not noticing the test case fail when merging that series, but TBH my expectations weren't that low back then. Won't happen again. Revert the following commits:539bca535d("x86/entry/64: Fix and clean up paranoid_exit")2c7b5ac5d5("Documentation/x86/64: Add documentation for GS/FS addressing mode")f987c955c7("x86/elf: Enumerate kernel FSGSBASE capability in AT_HWCAP2")2032f1f96e("x86/cpu: Enable FSGSBASE on 64bit by default and add a chicken bit")5bf0cab60e("x86/entry/64: Document GSBASE handling in the paranoid path")708078f657("x86/entry/64: Handle FSGSBASE enabled paranoid entry/exit")79e1932fa3("x86/entry/64: Introduce the FIND_PERCPU_BASE macro")1d07316b13("x86/entry/64: Switch CR3 before SWAPGS in paranoid entry")f60a83df45("x86/process/64: Use FSGSBASE instructions on thread copy and ptrace")1ab5f3f7fe("x86/process/64: Use FSBSBASE in switch_to() if available")a86b462513("x86/fsgsbase/64: Enable FSGSBASE instructions in helper functions")8b71340d70("x86/fsgsbase/64: Add intrinsics for FSGSBASE instructions")b64ed19b93("x86/cpu: Add 'unsafe_fsgsbase' to enable CR4.FSGSBASE") Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Ingo Molnar <mingo@kernel.org> Cc: Chang S. Bae <chang.seok.bae@intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ravi Shankar <ravi.v.shankar@intel.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: H. Peter Anvin <hpa@zytor.com>
312 lines
5.1 KiB
C
312 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Generate .byte code for some instructions not supported by old
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* binutils.
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*/
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#ifndef X86_ASM_INST_H
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#define X86_ASM_INST_H
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#ifdef __ASSEMBLY__
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#define REG_NUM_INVALID 100
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#define REG_TYPE_R32 0
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#define REG_TYPE_R64 1
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#define REG_TYPE_XMM 2
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#define REG_TYPE_INVALID 100
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.macro R32_NUM opd r32
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\opd = REG_NUM_INVALID
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.ifc \r32,%eax
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\opd = 0
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.endif
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.ifc \r32,%ecx
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\opd = 1
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.endif
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.ifc \r32,%edx
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\opd = 2
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.endif
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.ifc \r32,%ebx
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\opd = 3
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.endif
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.ifc \r32,%esp
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\opd = 4
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.endif
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.ifc \r32,%ebp
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\opd = 5
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.endif
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.ifc \r32,%esi
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\opd = 6
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.endif
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.ifc \r32,%edi
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\opd = 7
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.endif
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#ifdef CONFIG_X86_64
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.ifc \r32,%r8d
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\opd = 8
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.endif
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.ifc \r32,%r9d
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\opd = 9
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.endif
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.ifc \r32,%r10d
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\opd = 10
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.endif
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.ifc \r32,%r11d
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\opd = 11
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.endif
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.ifc \r32,%r12d
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\opd = 12
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.endif
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.ifc \r32,%r13d
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\opd = 13
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.endif
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.ifc \r32,%r14d
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\opd = 14
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.endif
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.ifc \r32,%r15d
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\opd = 15
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.endif
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#endif
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.endm
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.macro R64_NUM opd r64
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\opd = REG_NUM_INVALID
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#ifdef CONFIG_X86_64
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.ifc \r64,%rax
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\opd = 0
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.endif
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.ifc \r64,%rcx
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\opd = 1
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.endif
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.ifc \r64,%rdx
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\opd = 2
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.endif
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.ifc \r64,%rbx
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\opd = 3
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.endif
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.ifc \r64,%rsp
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\opd = 4
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.endif
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.ifc \r64,%rbp
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\opd = 5
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.endif
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.ifc \r64,%rsi
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\opd = 6
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.endif
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.ifc \r64,%rdi
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\opd = 7
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.endif
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.ifc \r64,%r8
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\opd = 8
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.endif
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.ifc \r64,%r9
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\opd = 9
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.endif
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.ifc \r64,%r10
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\opd = 10
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.endif
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.ifc \r64,%r11
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\opd = 11
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.endif
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.ifc \r64,%r12
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\opd = 12
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.endif
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.ifc \r64,%r13
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\opd = 13
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.endif
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.ifc \r64,%r14
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\opd = 14
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.endif
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.ifc \r64,%r15
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\opd = 15
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.endif
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#endif
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.endm
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.macro XMM_NUM opd xmm
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\opd = REG_NUM_INVALID
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.ifc \xmm,%xmm0
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\opd = 0
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.endif
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.ifc \xmm,%xmm1
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\opd = 1
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.endif
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.ifc \xmm,%xmm2
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\opd = 2
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.endif
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.ifc \xmm,%xmm3
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\opd = 3
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.endif
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.ifc \xmm,%xmm4
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\opd = 4
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.endif
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.ifc \xmm,%xmm5
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\opd = 5
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.endif
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.ifc \xmm,%xmm6
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\opd = 6
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.endif
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.ifc \xmm,%xmm7
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\opd = 7
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.endif
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.ifc \xmm,%xmm8
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\opd = 8
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.endif
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.ifc \xmm,%xmm9
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\opd = 9
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.endif
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.ifc \xmm,%xmm10
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\opd = 10
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.endif
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.ifc \xmm,%xmm11
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\opd = 11
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.endif
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.ifc \xmm,%xmm12
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\opd = 12
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.endif
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.ifc \xmm,%xmm13
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\opd = 13
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.endif
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.ifc \xmm,%xmm14
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\opd = 14
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.endif
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.ifc \xmm,%xmm15
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\opd = 15
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.endif
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.endm
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.macro REG_TYPE type reg
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R32_NUM reg_type_r32 \reg
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R64_NUM reg_type_r64 \reg
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XMM_NUM reg_type_xmm \reg
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.if reg_type_r64 <> REG_NUM_INVALID
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\type = REG_TYPE_R64
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.elseif reg_type_r32 <> REG_NUM_INVALID
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\type = REG_TYPE_R32
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.elseif reg_type_xmm <> REG_NUM_INVALID
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\type = REG_TYPE_XMM
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.else
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\type = REG_TYPE_INVALID
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.endif
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.endm
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.macro PFX_OPD_SIZE
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.byte 0x66
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.endm
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.macro PFX_REX opd1 opd2 W=0
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.if ((\opd1 | \opd2) & 8) || \W
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.byte 0x40 | ((\opd1 & 8) >> 3) | ((\opd2 & 8) >> 1) | (\W << 3)
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.endif
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.endm
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.macro MODRM mod opd1 opd2
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.byte \mod | (\opd1 & 7) | ((\opd2 & 7) << 3)
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.endm
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.macro PSHUFB_XMM xmm1 xmm2
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XMM_NUM pshufb_opd1 \xmm1
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XMM_NUM pshufb_opd2 \xmm2
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PFX_OPD_SIZE
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PFX_REX pshufb_opd1 pshufb_opd2
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.byte 0x0f, 0x38, 0x00
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MODRM 0xc0 pshufb_opd1 pshufb_opd2
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.endm
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.macro PCLMULQDQ imm8 xmm1 xmm2
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XMM_NUM clmul_opd1 \xmm1
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XMM_NUM clmul_opd2 \xmm2
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PFX_OPD_SIZE
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PFX_REX clmul_opd1 clmul_opd2
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.byte 0x0f, 0x3a, 0x44
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MODRM 0xc0 clmul_opd1 clmul_opd2
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.byte \imm8
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.endm
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.macro PEXTRD imm8 xmm gpr
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R32_NUM extrd_opd1 \gpr
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XMM_NUM extrd_opd2 \xmm
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PFX_OPD_SIZE
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PFX_REX extrd_opd1 extrd_opd2
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.byte 0x0f, 0x3a, 0x16
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MODRM 0xc0 extrd_opd1 extrd_opd2
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.byte \imm8
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.endm
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.macro AESKEYGENASSIST rcon xmm1 xmm2
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XMM_NUM aeskeygen_opd1 \xmm1
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XMM_NUM aeskeygen_opd2 \xmm2
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PFX_OPD_SIZE
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PFX_REX aeskeygen_opd1 aeskeygen_opd2
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.byte 0x0f, 0x3a, 0xdf
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MODRM 0xc0 aeskeygen_opd1 aeskeygen_opd2
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.byte \rcon
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.endm
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.macro AESIMC xmm1 xmm2
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XMM_NUM aesimc_opd1 \xmm1
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XMM_NUM aesimc_opd2 \xmm2
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PFX_OPD_SIZE
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PFX_REX aesimc_opd1 aesimc_opd2
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.byte 0x0f, 0x38, 0xdb
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MODRM 0xc0 aesimc_opd1 aesimc_opd2
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.endm
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.macro AESENC xmm1 xmm2
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XMM_NUM aesenc_opd1 \xmm1
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XMM_NUM aesenc_opd2 \xmm2
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PFX_OPD_SIZE
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PFX_REX aesenc_opd1 aesenc_opd2
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.byte 0x0f, 0x38, 0xdc
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MODRM 0xc0 aesenc_opd1 aesenc_opd2
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.endm
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.macro AESENCLAST xmm1 xmm2
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XMM_NUM aesenclast_opd1 \xmm1
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XMM_NUM aesenclast_opd2 \xmm2
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PFX_OPD_SIZE
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PFX_REX aesenclast_opd1 aesenclast_opd2
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.byte 0x0f, 0x38, 0xdd
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MODRM 0xc0 aesenclast_opd1 aesenclast_opd2
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.endm
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.macro AESDEC xmm1 xmm2
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XMM_NUM aesdec_opd1 \xmm1
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XMM_NUM aesdec_opd2 \xmm2
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PFX_OPD_SIZE
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PFX_REX aesdec_opd1 aesdec_opd2
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.byte 0x0f, 0x38, 0xde
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MODRM 0xc0 aesdec_opd1 aesdec_opd2
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.endm
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.macro AESDECLAST xmm1 xmm2
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XMM_NUM aesdeclast_opd1 \xmm1
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XMM_NUM aesdeclast_opd2 \xmm2
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PFX_OPD_SIZE
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PFX_REX aesdeclast_opd1 aesdeclast_opd2
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.byte 0x0f, 0x38, 0xdf
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MODRM 0xc0 aesdeclast_opd1 aesdeclast_opd2
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.endm
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.macro MOVQ_R64_XMM opd1 opd2
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REG_TYPE movq_r64_xmm_opd1_type \opd1
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.if movq_r64_xmm_opd1_type == REG_TYPE_XMM
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XMM_NUM movq_r64_xmm_opd1 \opd1
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R64_NUM movq_r64_xmm_opd2 \opd2
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.else
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R64_NUM movq_r64_xmm_opd1 \opd1
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XMM_NUM movq_r64_xmm_opd2 \opd2
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.endif
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PFX_OPD_SIZE
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PFX_REX movq_r64_xmm_opd1 movq_r64_xmm_opd2 1
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.if movq_r64_xmm_opd1_type == REG_TYPE_XMM
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.byte 0x0f, 0x7e
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.else
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.byte 0x0f, 0x6e
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.endif
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MODRM 0xc0 movq_r64_xmm_opd1 movq_r64_xmm_opd2
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.endm
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#endif
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#endif
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