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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8275b77a15
Enable power saving for RTS5250S as following steps: 1.Set 0xFE58 to enable clock power management. 2.Check cfg space whether support L1SS or not. 3.If support L1SS, set 0xFF03 to free clkreq. 4.When entering idle status, enable aspm and set parameters for L1SS and LTR. 5.Wnen entering run status, disable aspm and set parameters for L1SS and LTR. If entering L1SS mode successfully, electric current will be below 2mA. Signed-off-by: Rui Feng <rui_feng@realsil.com.cn> Signed-off-by: Lee Jones <lee.jones@linaro.org>
104 lines
3.7 KiB
C
104 lines
3.7 KiB
C
/* Driver for Realtek PCI-Express card reader
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*
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* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Author:
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* Wei WANG <wei_wang@realsil.com.cn>
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*/
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#ifndef __RTSX_PCR_H
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#define __RTSX_PCR_H
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#include <linux/mfd/rtsx_pci.h>
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#define MIN_DIV_N_PCR 80
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#define MAX_DIV_N_PCR 208
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#define RTS522A_PM_CTRL3 0xFF7E
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#define RTS524A_PME_FORCE_CTL 0xFF78
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#define RTS524A_PM_CTRL3 0xFF7E
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#define LTR_ACTIVE_LATENCY_DEF 0x883C
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#define LTR_IDLE_LATENCY_DEF 0x892C
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#define LTR_L1OFF_LATENCY_DEF 0x9003
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#define L1_SNOOZE_DELAY_DEF 1
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#define LTR_L1OFF_SSPWRGATE_5249_DEF 0xAF
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#define LTR_L1OFF_SSPWRGATE_5250_DEF 0xFF
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#define LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF 0xAC
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#define LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF 0xF8
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#define CMD_TIMEOUT_DEF 100
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#define ASPM_MASK_NEG 0xFC
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#define MASK_8_BIT_DEF 0xFF
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int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
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int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
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void rts5209_init_params(struct rtsx_pcr *pcr);
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void rts5229_init_params(struct rtsx_pcr *pcr);
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void rtl8411_init_params(struct rtsx_pcr *pcr);
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void rtl8402_init_params(struct rtsx_pcr *pcr);
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void rts5227_init_params(struct rtsx_pcr *pcr);
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void rts522a_init_params(struct rtsx_pcr *pcr);
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void rts5249_init_params(struct rtsx_pcr *pcr);
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void rts524a_init_params(struct rtsx_pcr *pcr);
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void rts525a_init_params(struct rtsx_pcr *pcr);
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void rtl8411b_init_params(struct rtsx_pcr *pcr);
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static inline u8 map_sd_drive(int idx)
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{
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u8 sd_drive[4] = {
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0x01, /* Type D */
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0x02, /* Type C */
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0x05, /* Type A */
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0x03 /* Type B */
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};
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return sd_drive[idx];
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}
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#define rtsx_vendor_setting_valid(reg) (!((reg) & 0x1000000))
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#define rts5209_vendor_setting1_valid(reg) (!((reg) & 0x80))
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#define rts5209_vendor_setting2_valid(reg) ((reg) & 0x80)
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#define rtsx_reg_to_aspm(reg) (((reg) >> 28) & 0x03)
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#define rtsx_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 26) & 0x03)
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#define rtsx_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x03)
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#define rtsx_reg_to_card_drive_sel(reg) ((((reg) >> 25) & 0x01) << 6)
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#define rtsx_reg_check_reverse_socket(reg) ((reg) & 0x4000)
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#define rts5209_reg_to_aspm(reg) (((reg) >> 5) & 0x03)
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#define rts5209_reg_check_ms_pmos(reg) (!((reg) & 0x08))
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#define rts5209_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 3) & 0x07)
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#define rts5209_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x07)
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#define rts5209_reg_to_card_drive_sel(reg) ((reg) >> 8)
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#define rtl8411_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x07)
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#define rtl8411b_reg_to_sd30_drive_sel_3v3(reg) ((reg) & 0x03)
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#define set_pull_ctrl_tables(pcr, __device) \
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do { \
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pcr->sd_pull_ctl_enable_tbl = __device##_sd_pull_ctl_enable_tbl; \
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pcr->sd_pull_ctl_disable_tbl = __device##_sd_pull_ctl_disable_tbl; \
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pcr->ms_pull_ctl_enable_tbl = __device##_ms_pull_ctl_enable_tbl; \
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pcr->ms_pull_ctl_disable_tbl = __device##_ms_pull_ctl_disable_tbl; \
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} while (0)
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/* generic operations */
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int rtsx_gops_pm_reset(struct rtsx_pcr *pcr);
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int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency);
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int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val);
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#endif
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