mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c5d9da4aab
NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma". Tegra114 DMA controller is not compatible with Tegra30/Tegra20 DMA controller driver as in Tegra114, the global pause also clock gate the DMA register and hence it iw not possible to write the DMA register with global pause. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed DT node order] Signed-off-by: Stephen Warren <swarren@nvidia.com>
240 lines
4.9 KiB
Plaintext
240 lines
4.9 KiB
Plaintext
/include/ "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra114";
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interrupt-parent = <&gic>;
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gic: interrupt-controller {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x50041000 0x1000>,
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<0x50042000 0x1000>,
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<0x50044000 0x2000>,
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<0x50046000 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04
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0 121 0x04
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0 122 0x04>;
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clocks = <&tegra_car 5>;
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};
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tegra_car: clock {
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compatible = "nvidia,tegra114-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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apbdma: dma {
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compatible = "nvidia,tegra114-apbdma";
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reg = <0x6000a000 0x1400>;
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interrupts = <0 104 0x04
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0 105 0x04
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0 106 0x04
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0 107 0x04
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0 108 0x04
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0 109 0x04
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0 110 0x04
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0 111 0x04
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0 112 0x04
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0 113 0x04
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0 114 0x04
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0 115 0x04
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0 116 0x04
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0 117 0x04
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0 118 0x04
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0 119 0x04
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0 128 0x04
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0 129 0x04
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0 130 0x04
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0 131 0x04
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0 132 0x04
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0 133 0x04
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0 134 0x04
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0 135 0x04
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0 136 0x04
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0 137 0x04
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0 138 0x04
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0 139 0x04
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0 140 0x04
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0 141 0x04
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0 142 0x04
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0 143 0x04>;
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clocks = <&tegra_car 34>;
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};
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ahb: ahb {
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compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
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reg = <0x6000c004 0x14c>;
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};
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gpio: gpio {
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compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <0 32 0x04
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0 33 0x04
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0 34 0x04
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0 35 0x04
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0 55 0x04
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0 87 0x04
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0 89 0x04
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0 125 0x04>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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pinmux: pinmux {
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compatible = "nvidia,tegra114-pinmux";
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reg = <0x70000868 0x148 /* Pad control registers */
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0x70003000 0x40c>; /* Mux registers */
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};
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serial@70006000 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <0 36 0x04>;
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status = "disabled";
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clocks = <&tegra_car 6>;
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};
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serial@70006040 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = <0 37 0x04>;
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status = "disabled";
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clocks = <&tegra_car 192>;
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};
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serial@70006200 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = <0 46 0x04>;
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status = "disabled";
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clocks = <&tegra_car 55>;
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};
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serial@70006300 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = <0 90 0x04>;
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status = "disabled";
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clocks = <&tegra_car 65>;
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};
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pwm: pwm {
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compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
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reg = <0x7000a000 0x100>;
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#pwm-cells = <2>;
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clocks = <&tegra_car 17>;
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status = "disabled";
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};
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rtc {
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compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
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reg = <0x7000e000 0x100>;
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interrupts = <0 2 0x04>;
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clocks = <&tegra_car 4>;
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};
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pmc {
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compatible = "nvidia,tegra114-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car 261>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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};
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iommu {
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compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
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reg = <0x7000f010 0x02c
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0x7000f1f0 0x010
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0x7000f228 0x074>;
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nvidia,#asids = <4>;
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dma-window = <0 0x40000000>;
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nvidia,swgroups = <0x18659fe>;
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nvidia,ahb = <&ahb>;
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};
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sdhci@78000000 {
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compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
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reg = <0x78000000 0x200>;
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interrupts = <0 14 0x04>;
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clocks = <&tegra_car 14>;
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status = "disable";
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};
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sdhci@78000200 {
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compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
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reg = <0x78000200 0x200>;
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interrupts = <0 15 0x04>;
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clocks = <&tegra_car 9>;
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status = "disable";
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};
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sdhci@78000400 {
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compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
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reg = <0x78000400 0x200>;
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interrupts = <0 19 0x04>;
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clocks = <&tegra_car 69>;
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status = "disable";
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};
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sdhci@78000600 {
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compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
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reg = <0x78000600 0x200>;
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interrupts = <0 31 0x04>;
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clocks = <&tegra_car 15>;
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status = "disable";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <3>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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};
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