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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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510c0ffdd4
Adds the counter-32k timers nodes present in OMAP2/3/4 devices and device-tree binding documentation for OMAP counter-32k. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
402 lines
8.6 KiB
Plaintext
402 lines
8.6 KiB
Plaintext
/*
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* Device Tree Source for OMAP3 SoC
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "ti,omap3430", "ti,omap3";
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interrupt-parent = <&intc>;
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aliases {
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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};
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cpus {
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cpu@0 {
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compatible = "arm,cortex-a8";
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};
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};
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/*
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* The soc node represents the soc top level view. It is uses for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap3-mpu";
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ti,hwmods = "mpu";
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};
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iva {
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compatible = "ti,iva2.2";
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ti,hwmods = "iva";
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dsp {
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compatible = "ti,omap3-c64";
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};
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};
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};
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/*
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* XXX: Use a flat representation of the OMAP3 interconnect.
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* The real OMAP interconnect network is quite complex.
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* Since that will not bring real advantage to represent that in DT for
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* the moment, just use a fake OCP bus entry to represent the whole bus
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* hierarchy.
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*/
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ocp {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main";
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counter32k: counter@48320000 {
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compatible = "ti,omap-counter32k";
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reg = <0x48320000 0x20>;
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ti,hwmods = "counter_32k";
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};
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intc: interrupt-controller@48200000 {
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compatible = "ti,omap2-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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ti,intc-size = <96>;
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reg = <0x48200000 0x1000>;
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};
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omap3_pmx_core: pinmux@48002030 {
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compatible = "ti,omap3-padconf", "pinctrl-single";
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reg = <0x48002030 0x05cc>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0x7fff>;
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};
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omap3_pmx_wkup: pinmux@0x48002a58 {
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compatible = "ti,omap3-padconf", "pinctrl-single";
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reg = <0x48002a58 0x5c>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0x7fff>;
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};
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gpio1: gpio@48310000 {
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compatible = "ti,omap3-gpio";
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ti,hwmods = "gpio1";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio2: gpio@49050000 {
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compatible = "ti,omap3-gpio";
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ti,hwmods = "gpio2";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio3: gpio@49052000 {
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compatible = "ti,omap3-gpio";
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ti,hwmods = "gpio3";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio4: gpio@49054000 {
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compatible = "ti,omap3-gpio";
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ti,hwmods = "gpio4";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio5: gpio@49056000 {
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compatible = "ti,omap3-gpio";
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ti,hwmods = "gpio5";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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gpio6: gpio@49058000 {
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compatible = "ti,omap3-gpio";
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ti,hwmods = "gpio6";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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uart1: serial@4806a000 {
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compatible = "ti,omap3-uart";
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ti,hwmods = "uart1";
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clock-frequency = <48000000>;
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};
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uart2: serial@4806c000 {
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compatible = "ti,omap3-uart";
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ti,hwmods = "uart2";
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clock-frequency = <48000000>;
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};
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uart3: serial@49020000 {
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compatible = "ti,omap3-uart";
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ti,hwmods = "uart3";
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clock-frequency = <48000000>;
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};
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i2c1: i2c@48070000 {
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compatible = "ti,omap3-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c1";
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};
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i2c2: i2c@48072000 {
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compatible = "ti,omap3-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c2";
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};
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i2c3: i2c@48060000 {
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compatible = "ti,omap3-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c3";
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};
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mcspi1: spi@48098000 {
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compatible = "ti,omap2-mcspi";
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "mcspi1";
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ti,spi-num-cs = <4>;
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};
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mcspi2: spi@4809a000 {
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compatible = "ti,omap2-mcspi";
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "mcspi2";
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ti,spi-num-cs = <2>;
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};
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mcspi3: spi@480b8000 {
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compatible = "ti,omap2-mcspi";
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "mcspi3";
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ti,spi-num-cs = <2>;
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};
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mcspi4: spi@480ba000 {
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compatible = "ti,omap2-mcspi";
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "mcspi4";
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ti,spi-num-cs = <1>;
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};
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mmc1: mmc@4809c000 {
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compatible = "ti,omap3-hsmmc";
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ti,hwmods = "mmc1";
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ti,dual-volt;
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};
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mmc2: mmc@480b4000 {
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compatible = "ti,omap3-hsmmc";
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ti,hwmods = "mmc2";
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};
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mmc3: mmc@480ad000 {
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compatible = "ti,omap3-hsmmc";
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ti,hwmods = "mmc3";
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};
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wdt2: wdt@48314000 {
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compatible = "ti,omap3-wdt";
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ti,hwmods = "wd_timer2";
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};
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mcbsp1: mcbsp@48074000 {
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compatible = "ti,omap3-mcbsp";
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reg = <0x48074000 0xff>;
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reg-names = "mpu";
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interrupts = <16>, /* OCP compliant interrupt */
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<59>, /* TX interrupt */
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<60>; /* RX interrupt */
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interrupt-names = "common", "tx", "rx";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp1";
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};
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mcbsp2: mcbsp@49022000 {
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compatible = "ti,omap3-mcbsp";
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reg = <0x49022000 0xff>,
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<0x49028000 0xff>;
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reg-names = "mpu", "sidetone";
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interrupts = <17>, /* OCP compliant interrupt */
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<62>, /* TX interrupt */
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<63>, /* RX interrupt */
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<4>; /* Sidetone */
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interrupt-names = "common", "tx", "rx", "sidetone";
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ti,buffer-size = <1280>;
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ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
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};
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mcbsp3: mcbsp@49024000 {
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compatible = "ti,omap3-mcbsp";
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reg = <0x49024000 0xff>,
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<0x4902a000 0xff>;
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reg-names = "mpu", "sidetone";
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interrupts = <22>, /* OCP compliant interrupt */
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<89>, /* TX interrupt */
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<90>, /* RX interrupt */
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<5>; /* Sidetone */
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interrupt-names = "common", "tx", "rx", "sidetone";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
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};
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mcbsp4: mcbsp@49026000 {
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compatible = "ti,omap3-mcbsp";
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reg = <0x49026000 0xff>;
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reg-names = "mpu";
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interrupts = <23>, /* OCP compliant interrupt */
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<54>, /* TX interrupt */
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<55>; /* RX interrupt */
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interrupt-names = "common", "tx", "rx";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp4";
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};
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mcbsp5: mcbsp@48096000 {
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compatible = "ti,omap3-mcbsp";
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reg = <0x48096000 0xff>;
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reg-names = "mpu";
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interrupts = <27>, /* OCP compliant interrupt */
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<81>, /* TX interrupt */
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<82>; /* RX interrupt */
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interrupt-names = "common", "tx", "rx";
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ti,buffer-size = <128>;
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ti,hwmods = "mcbsp5";
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};
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timer1: timer@48318000 {
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compatible = "ti,omap2-timer";
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reg = <0x48318000 0x400>;
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interrupts = <37>;
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ti,hwmods = "timer1";
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ti,timer-alwon;
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};
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timer2: timer@49032000 {
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compatible = "ti,omap2-timer";
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reg = <0x49032000 0x400>;
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interrupts = <38>;
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ti,hwmods = "timer2";
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};
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timer3: timer@49034000 {
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compatible = "ti,omap2-timer";
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reg = <0x49034000 0x400>;
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interrupts = <39>;
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ti,hwmods = "timer3";
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};
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timer4: timer@49036000 {
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compatible = "ti,omap2-timer";
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reg = <0x49036000 0x400>;
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interrupts = <40>;
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ti,hwmods = "timer4";
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};
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timer5: timer@49038000 {
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compatible = "ti,omap2-timer";
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reg = <0x49038000 0x400>;
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interrupts = <41>;
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ti,hwmods = "timer5";
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ti,timer-dsp;
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};
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timer6: timer@4903a000 {
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compatible = "ti,omap2-timer";
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reg = <0x4903a000 0x400>;
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interrupts = <42>;
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ti,hwmods = "timer6";
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ti,timer-dsp;
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};
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timer7: timer@4903c000 {
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compatible = "ti,omap2-timer";
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reg = <0x4903c000 0x400>;
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interrupts = <43>;
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ti,hwmods = "timer7";
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ti,timer-dsp;
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};
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timer8: timer@4903e000 {
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compatible = "ti,omap2-timer";
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reg = <0x4903e000 0x400>;
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interrupts = <44>;
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ti,hwmods = "timer8";
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ti,timer-pwm;
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ti,timer-dsp;
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};
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timer9: timer@49040000 {
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compatible = "ti,omap2-timer";
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reg = <0x49040000 0x400>;
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interrupts = <45>;
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ti,hwmods = "timer9";
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ti,timer-pwm;
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};
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timer10: timer@48086000 {
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compatible = "ti,omap2-timer";
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reg = <0x48086000 0x400>;
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interrupts = <46>;
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ti,hwmods = "timer10";
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ti,timer-pwm;
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};
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timer11: timer@48088000 {
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compatible = "ti,omap2-timer";
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reg = <0x48088000 0x400>;
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interrupts = <47>;
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ti,hwmods = "timer11";
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ti,timer-pwm;
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};
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timer12: timer@48304000 {
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compatible = "ti,omap2-timer";
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reg = <0x48304000 0x400>;
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interrupts = <95>;
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ti,hwmods = "timer12";
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ti,timer-alwon;
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ti,timer-secure;
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};
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};
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};
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