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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 18:20:53 +07:00
0545c798e9
According to fsl,imx53-pinctrl.txt, the pin number of DISP1_DAT_21 should be 545, while 543 is IPU_CSI0_D_3. Along with the change, one duplication of DISP1_DAT_0 in disp1-grp1 is removed. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
130 lines
2.7 KiB
Plaintext
130 lines
2.7 KiB
Plaintext
/*
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* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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/include/ "imx53-tqma53.dtsi"
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/ {
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model = "TQ MBa53 starter kit";
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compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
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};
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&iomuxc {
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lvds1 {
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pinctrl_lvds1_1: lvds1-grp1 {
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fsl,pins = <730 0x10000 /* LVDS0_TX3 */
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732 0x10000 /* LVDS0_CLK */
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734 0x10000 /* LVDS0_TX2 */
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736 0x10000 /* LVDS0_TX1 */
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738 0x10000>; /* LVDS0_TX0 */
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};
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pinctrl_lvds1_2: lvds1-grp2 {
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fsl,pins = <720 0x10000 /* LVDS1_TX3 */
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722 0x10000 /* LVDS1_TX2 */
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724 0x10000 /* LVDS1_CLK */
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726 0x10000 /* LVDS1_TX1 */
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728 0x10000>; /* LVDS1_TX0 */
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};
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};
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disp1 {
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pinctrl_disp1_1: disp1-grp1 {
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fsl,pins = <689 0x10000 /* DISP1_DRDY */
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482 0x10000 /* DISP1_HSYNC */
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489 0x10000 /* DISP1_VSYNC */
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515 0x10000 /* DISP1_DAT_22 */
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523 0x10000 /* DISP1_DAT_23 */
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545 0x10000 /* DISP1_DAT_21 */
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553 0x10000 /* DISP1_DAT_20 */
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558 0x10000 /* DISP1_DAT_19 */
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564 0x10000 /* DISP1_DAT_18 */
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570 0x10000 /* DISP1_DAT_17 */
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575 0x10000 /* DISP1_DAT_16 */
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580 0x10000 /* DISP1_DAT_15 */
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585 0x10000 /* DISP1_DAT_14 */
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590 0x10000 /* DISP1_DAT_13 */
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595 0x10000 /* DISP1_DAT_12 */
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628 0x10000 /* DISP1_DAT_11 */
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634 0x10000 /* DISP1_DAT_10 */
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639 0x10000 /* DISP1_DAT_9 */
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644 0x10000 /* DISP1_DAT_8 */
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649 0x10000 /* DISP1_DAT_7 */
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654 0x10000 /* DISP1_DAT_6 */
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659 0x10000 /* DISP1_DAT_5 */
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664 0x10000 /* DISP1_DAT_4 */
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669 0x10000 /* DISP1_DAT_3 */
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674 0x10000 /* DISP1_DAT_2 */
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679 0x10000 /* DISP1_DAT_1 */
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684 0x10000>; /* DISP1_DAT_0 */
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};
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};
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};
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&cspi {
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status = "okay";
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};
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&i2c2 {
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codec: sgtl5000@a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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};
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expander: pca9554@20 {
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compatible = "pca9554";
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reg = <0x20>;
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interrupts = <109>;
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};
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sensor2: lm75@49 {
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compatible = "lm75";
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reg = <0x49>;
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};
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};
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&fec {
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status = "okay";
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};
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&esdhc2 {
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status = "okay";
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};
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&uart3 {
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status = "okay";
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};
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&ecspi1 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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&can1 {
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status = "okay";
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};
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&can2 {
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status = "okay";
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};
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&i2c3 {
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status = "okay";
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};
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