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466b3cf17e
The dma-cells value in the example was 2 instead of 1. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
55 lines
1.7 KiB
Plaintext
55 lines
1.7 KiB
Plaintext
* Atmel Extensible Direct Memory Access Controller (XDMAC)
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* XDMA Controller
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Required properties:
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- compatible: Should be "atmel,<chip>-dma".
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<chip> compatible description:
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- sama5d4: first SoC adding the XDMAC
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- reg: Should contain DMA registers location and length.
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- interrupts: Should contain DMA interrupt.
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- #dma-cells: Must be <1>, used to represent the number of integer cells in
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the dmas property of client devices.
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- The 1st cell specifies the channel configuration register:
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- bit 13: SIF, source interface identifier, used to get the memory
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interface identifier,
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- bit 14: DIF, destination interface identifier, used to get the peripheral
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interface identifier,
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- bit 30-24: PERID, peripheral identifier.
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Example:
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dma1: dma-controller@f0004000 {
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compatible = "atmel,sama5d4-dma";
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reg = <0xf0004000 0x200>;
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interrupts = <50 4 0>;
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#dma-cells = <1>;
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};
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* DMA clients
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DMA clients connected to the Atmel XDMA controller must use the format
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described in the dma.txt file, using a one-cell specifier for each channel.
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The two cells in order are:
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1. A phandle pointing to the DMA controller.
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2. Channel configuration register. Configurable fields are:
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- bit 13: SIF, source interface identifier, used to get the memory
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interface identifier,
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- bit 14: DIF, destination interface identifier, used to get the peripheral
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interface identifier,
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- bit 30-24: PERID, peripheral identifier.
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Example:
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i2c2: i2c@f8024000 {
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compatible = "atmel,at91sam9x5-i2c";
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reg = <0xf8024000 0x4000>;
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interrupts = <34 4 6>;
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dmas = <&dma1
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(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
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| AT91_XDMAC_DT_PERID(6))>,
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<&dma1
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(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
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| AT91_XDMAC_DT_PERID(7))>;
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dma-names = "tx", "rx";
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};
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