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c8ce8007e5
Add a device node for the Watchdog Timer (WDT) controller on the Renesas R-Car M3-W (r8a7796) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
139 lines
3.4 KiB
Plaintext
139 lines
3.4 KiB
Plaintext
/*
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* Device Tree Source for the r8a7796 SoC
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*
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* Copyright (C) 2016 Renesas Electronics Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7796-sysc.h>
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/ {
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compatible = "renesas,r8a7796";
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* 1 core only at this point */
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a57_0: cpu@0 {
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compatible = "arm,cortex-a57", "arm,armv8";
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reg = <0x0>;
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device_type = "cpu";
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power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
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next-level-cache = <&L2_CA57>;
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enable-method = "psci";
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};
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L2_CA57: cache-controller@0 {
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compatible = "cache";
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reg = <0>;
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power-domains = <&sysc R8A7796_PD_CA57_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@f1010000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xf1010000 0 0x1000>,
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<0x0 0xf1020000 0 0x20000>,
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<0x0 0xf1040000 0 0x20000>,
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<0x0 0xf1060000 0 0x20000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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};
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wdt0: watchdog@e6020000 {
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compatible = "renesas,r8a7796-wdt",
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"renesas,rcar-gen3-wdt";
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reg = <0 0xe6020000 0 0x0c>;
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clocks = <&cpg CPG_MOD 402>;
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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status = "disabled";
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7796-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7796-sysc";
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reg = <0 0xe6180000 0 0x0400>;
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#power-domain-cells = <1>;
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};
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scif2: serial@e6e88000 {
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compatible = "renesas,scif-r8a7796",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6e88000 0 64>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 310>,
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<&cpg CPG_CORE R8A7796_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
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status = "disabled";
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};
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};
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};
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