mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 00:06:51 +07:00
f7d569c1e6
The bogus 'device_type = "pci"' confuses dtc, causing lots of totally unrelated warnings. After fixing that, real warnings like arch/arm/boot/dts/r8a7790-lager.dtb: Warning (pci_device_reg): Node /pci@ee090000/usb@0,1 PCI unit address format error, expected "1,0" are left. Correct the unit-addresses and reg properties of the subnodes to fix these. Signed-off-by: Rob Herring <robh@kernel.org> [geert: Improve description] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
1640 lines
49 KiB
Plaintext
1640 lines
49 KiB
Plaintext
/*
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* Device Tree Source for the r8a7794 SoC
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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* Copyright (C) 2014 Ulrich Hecht
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7794-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/r8a7794-sysc.h>
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/ {
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compatible = "renesas,r8a7794";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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spi0 = &qspi;
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vin0 = &vin0;
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vin1 = &vin1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0>;
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clock-frequency = <1000000000>;
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clocks = <&z2_clk>;
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power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
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next-level-cache = <&L2_CA7>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <1>;
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clock-frequency = <1000000000>;
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power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
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next-level-cache = <&L2_CA7>;
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};
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L2_CA7: cache-controller-0 {
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compatible = "cache";
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power-domains = <&sysc R8A7794_PD_CA7_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x2000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&mstp4_clks R8A7794_CLK_INTC_SYS>;
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clock-names = "clk";
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 26>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 28>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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};
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gpio6: gpio@e6055400 {
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compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
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reg = <0 0xe6055400 0 0x50>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 26>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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};
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cmt0: timer@ffca0000 {
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compatible = "renesas,cmt-48-gen2";
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reg = <0 0xffca0000 0 0x1004>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
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clock-names = "fck";
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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renesas,channels-mask = <0x60>;
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status = "disabled";
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};
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cmt1: timer@e6130000 {
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compatible = "renesas,cmt-48-gen2";
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reg = <0 0xe6130000 0 0x1004>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
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clock-names = "fck";
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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renesas,channels-mask = <0xff>;
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status = "disabled";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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irqc0: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7794", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a7794";
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reg = <0 0xe6060000 0 0x11c>;
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};
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
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reg = <0 0xe6700000 0 0x20000>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
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clock-names = "fck";
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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dmac1: dma-controller@e6720000 {
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compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
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reg = <0 0xe6720000 0 0x20000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
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clock-names = "fck";
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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audma0: dma-controller@ec700000 {
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compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
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reg = <0 0xec700000 0 0x10000>;
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interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
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"ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
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"ch12";
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clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>;
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clock-names = "fck";
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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#dma-cells = <1>;
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dma-channels = <13>;
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};
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scifa0: serial@e6c40000 {
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compatible = "renesas,scifa-r8a7794",
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"renesas,rcar-gen2-scifa", "renesas,scifa";
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reg = <0 0xe6c40000 0 64>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
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clock-names = "fck";
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dmas = <&dmac0 0x21>, <&dmac0 0x22>,
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<&dmac1 0x21>, <&dmac1 0x22>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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status = "disabled";
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};
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scifa1: serial@e6c50000 {
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compatible = "renesas,scifa-r8a7794",
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"renesas,rcar-gen2-scifa", "renesas,scifa";
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reg = <0 0xe6c50000 0 64>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
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clock-names = "fck";
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dmas = <&dmac0 0x25>, <&dmac0 0x26>,
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<&dmac1 0x25>, <&dmac1 0x26>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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status = "disabled";
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};
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scifa2: serial@e6c60000 {
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compatible = "renesas,scifa-r8a7794",
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"renesas,rcar-gen2-scifa", "renesas,scifa";
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reg = <0 0xe6c60000 0 64>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
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clock-names = "fck";
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dmas = <&dmac0 0x27>, <&dmac0 0x28>,
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<&dmac1 0x27>, <&dmac1 0x28>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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status = "disabled";
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};
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scifa3: serial@e6c70000 {
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compatible = "renesas,scifa-r8a7794",
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"renesas,rcar-gen2-scifa", "renesas,scifa";
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reg = <0 0xe6c70000 0 64>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
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clock-names = "fck";
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dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
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<&dmac1 0x1b>, <&dmac1 0x1c>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
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status = "disabled";
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};
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scifa4: serial@e6c78000 {
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compatible = "renesas,scifa-r8a7794",
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"renesas,rcar-gen2-scifa", "renesas,scifa";
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reg = <0 0xe6c78000 0 64>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
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clock-names = "fck";
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dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
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<&dmac1 0x1f>, <&dmac1 0x20>;
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dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa5: serial@e6c80000 {
|
|
compatible = "renesas,scifa-r8a7794",
|
|
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
|
reg = <0 0xe6c80000 0 64>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
|
|
clock-names = "fck";
|
|
dmas = <&dmac0 0x23>, <&dmac0 0x24>,
|
|
<&dmac1 0x23>, <&dmac1 0x24>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifb0: serial@e6c20000 {
|
|
compatible = "renesas,scifb-r8a7794",
|
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
|
reg = <0 0xe6c20000 0 0x100>;
|
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
|
|
clock-names = "fck";
|
|
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
|
|
<&dmac1 0x3d>, <&dmac1 0x3e>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifb1: serial@e6c30000 {
|
|
compatible = "renesas,scifb-r8a7794",
|
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
|
reg = <0 0xe6c30000 0 0x100>;
|
|
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
|
|
clock-names = "fck";
|
|
dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
|
|
<&dmac1 0x19>, <&dmac1 0x1a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifb2: serial@e6ce0000 {
|
|
compatible = "renesas,scifb-r8a7794",
|
|
"renesas,rcar-gen2-scifb", "renesas,scifb";
|
|
reg = <0 0xe6ce0000 0 0x100>;
|
|
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
|
|
clock-names = "fck";
|
|
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
|
|
<&dmac1 0x1d>, <&dmac1 0x1e>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif0: serial@e6e60000 {
|
|
compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
|
|
"renesas,scif";
|
|
reg = <0 0xe6e60000 0 64>;
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
|
|
<&dmac1 0x29>, <&dmac1 0x2a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif1: serial@e6e68000 {
|
|
compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
|
|
"renesas,scif";
|
|
reg = <0 0xe6e68000 0 64>;
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
|
|
<&dmac1 0x2d>, <&dmac1 0x2e>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif2: serial@e6e58000 {
|
|
compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
|
|
"renesas,scif";
|
|
reg = <0 0xe6e58000 0 64>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
|
|
<&dmac1 0x2b>, <&dmac1 0x2c>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@e6ea8000 {
|
|
compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
|
|
"renesas,scif";
|
|
reg = <0 0xe6ea8000 0 64>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
|
|
<&dmac1 0x2f>, <&dmac1 0x30>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif4: serial@e6ee0000 {
|
|
compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
|
|
"renesas,scif";
|
|
reg = <0 0xe6ee0000 0 64>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
|
|
<&dmac1 0xfb>, <&dmac1 0xfc>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif5: serial@e6ee8000 {
|
|
compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
|
|
"renesas,scif";
|
|
reg = <0 0xe6ee8000 0 64>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
|
|
<&dmac1 0xfd>, <&dmac1 0xfe>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif0: serial@e62c0000 {
|
|
compatible = "renesas,hscif-r8a7794",
|
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
|
reg = <0 0xe62c0000 0 96>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
|
|
<&dmac1 0x39>, <&dmac1 0x3a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif1: serial@e62c8000 {
|
|
compatible = "renesas,hscif-r8a7794",
|
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
|
reg = <0 0xe62c8000 0 96>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
|
|
<&dmac1 0x4d>, <&dmac1 0x4e>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif2: serial@e62d0000 {
|
|
compatible = "renesas,hscif-r8a7794",
|
|
"renesas,rcar-gen2-hscif", "renesas,hscif";
|
|
reg = <0 0xe62d0000 0 96>;
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
|
|
<&dmac1 0x3b>, <&dmac1 0x3c>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ether: ethernet@ee700000 {
|
|
compatible = "renesas,ether-r8a7794";
|
|
reg = <0 0xee700000 0 0x400>;
|
|
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
phy-mode = "rmii";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
avb: ethernet@e6800000 {
|
|
compatible = "renesas,etheravb-r8a7794",
|
|
"renesas,etheravb-rcar-gen2";
|
|
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
|
|
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* The memory map in the User's Manual maps the cores to bus numbers */
|
|
i2c0: i2c@e6508000 {
|
|
compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6508000 0 0x40>;
|
|
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@e6518000 {
|
|
compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6518000 0 0x40>;
|
|
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@e6530000 {
|
|
compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6530000 0 0x40>;
|
|
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@e6540000 {
|
|
compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6540000 0 0x40>;
|
|
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@e6520000 {
|
|
compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6520000 0 0x40>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@e6528000 {
|
|
compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
|
|
reg = <0 0xe6528000 0 0x40>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@e6500000 {
|
|
compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
|
|
"renesas,rmobile-iic";
|
|
reg = <0 0xe6500000 0 0x425>;
|
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
|
|
dmas = <&dmac0 0x61>, <&dmac0 0x62>,
|
|
<&dmac1 0x61>, <&dmac1 0x62>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c@e6510000 {
|
|
compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
|
|
"renesas,rmobile-iic";
|
|
reg = <0 0xe6510000 0 0x425>;
|
|
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
|
|
dmas = <&dmac0 0x65>, <&dmac0 0x66>,
|
|
<&dmac1 0x65>, <&dmac1 0x66>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmcif0: mmc@ee200000 {
|
|
compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
|
|
reg = <0 0xee200000 0 0x80>;
|
|
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
|
|
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
|
|
<&dmac1 0xd1>, <&dmac1 0xd2>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi0: sd@ee100000 {
|
|
compatible = "renesas,sdhi-r8a7794";
|
|
reg = <0 0xee100000 0 0x328>;
|
|
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
|
|
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
|
|
<&dmac1 0xcd>, <&dmac1 0xce>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
max-frequency = <195000000>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi1: sd@ee140000 {
|
|
compatible = "renesas,sdhi-r8a7794";
|
|
reg = <0 0xee140000 0 0x100>;
|
|
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
|
|
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
|
|
<&dmac1 0xc1>, <&dmac1 0xc2>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
max-frequency = <97500000>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi2: sd@ee160000 {
|
|
compatible = "renesas,sdhi-r8a7794";
|
|
reg = <0 0xee160000 0 0x100>;
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
|
|
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
|
|
<&dmac1 0xd3>, <&dmac1 0xd4>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
max-frequency = <97500000>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qspi: spi@e6b10000 {
|
|
compatible = "renesas,qspi-r8a7794", "renesas,qspi";
|
|
reg = <0 0xe6b10000 0 0x2c>;
|
|
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
|
|
dmas = <&dmac0 0x17>, <&dmac0 0x18>,
|
|
<&dmac1 0x17>, <&dmac1 0x18>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin0: video@e6ef0000 {
|
|
compatible = "renesas,vin-r8a7794";
|
|
reg = <0 0xe6ef0000 0 0x1000>;
|
|
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin1: video@e6ef1000 {
|
|
compatible = "renesas,vin-r8a7794";
|
|
reg = <0 0xe6ef1000 0 0x1000>;
|
|
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pci0: pci@ee090000 {
|
|
compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
|
|
device_type = "pci";
|
|
reg = <0 0xee090000 0 0xc00>,
|
|
<0 0xee080000 0 0x1100>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
|
|
bus-range = <0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
|
|
interrupt-map-mask = <0xff00 0 0 0x7>;
|
|
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
|
|
0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
|
|
0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
usb@1,0 {
|
|
reg = <0x800 0 0 0 0>;
|
|
phys = <&usb0 0>;
|
|
phy-names = "usb";
|
|
};
|
|
|
|
usb@2,0 {
|
|
reg = <0x1000 0 0 0 0>;
|
|
phys = <&usb0 0>;
|
|
phy-names = "usb";
|
|
};
|
|
};
|
|
|
|
pci1: pci@ee0d0000 {
|
|
compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
|
|
device_type = "pci";
|
|
reg = <0 0xee0d0000 0 0xc00>,
|
|
<0 0xee0c0000 0 0x1100>;
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
|
|
bus-range = <1 1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
|
|
interrupt-map-mask = <0xff00 0 0 0x7>;
|
|
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
|
|
0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
|
|
0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
usb@1,0 {
|
|
reg = <0x10800 0 0 0 0>;
|
|
phys = <&usb2 0>;
|
|
phy-names = "usb";
|
|
};
|
|
|
|
usb@2,0 {
|
|
reg = <0x11000 0 0 0 0>;
|
|
phys = <&usb2 0>;
|
|
phy-names = "usb";
|
|
};
|
|
};
|
|
|
|
hsusb: usb@e6590000 {
|
|
compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
|
|
reg = <0 0xe6590000 0 0x100>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
renesas,buswait = <4>;
|
|
phys = <&usb0 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbphy: usb-phy@e6590100 {
|
|
compatible = "renesas,usb-phy-r8a7794",
|
|
"renesas,rcar-gen2-usb-phy";
|
|
reg = <0 0xe6590100 0 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
|
|
clock-names = "usbhs";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
|
|
usb0: usb-channel@0 {
|
|
reg = <0>;
|
|
#phy-cells = <1>;
|
|
};
|
|
usb2: usb-channel@2 {
|
|
reg = <2>;
|
|
#phy-cells = <1>;
|
|
};
|
|
};
|
|
|
|
vsp1@fe928000 {
|
|
compatible = "renesas,vsp1";
|
|
reg = <0 0xfe928000 0 0x8000>;
|
|
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
};
|
|
|
|
vsp1@fe930000 {
|
|
compatible = "renesas,vsp1";
|
|
reg = <0 0xfe930000 0 0x8000>;
|
|
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>;
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
};
|
|
|
|
du: display@feb00000 {
|
|
compatible = "renesas,du-r8a7794";
|
|
reg = <0 0xfeb00000 0 0x40000>;
|
|
reg-names = "du";
|
|
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7794_CLK_DU0>,
|
|
<&mstp7_clks R8A7794_CLK_DU1>;
|
|
clock-names = "du.0", "du.1";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
du_out_rgb0: endpoint {
|
|
};
|
|
};
|
|
port@1 {
|
|
reg = <1>;
|
|
du_out_rgb1: endpoint {
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
can0: can@e6e80000 {
|
|
compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
|
|
reg = <0 0xe6e80000 0 0x1000>;
|
|
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
|
|
<&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
|
|
clock-names = "clkp1", "clkp2", "can_clk";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can1: can@e6e88000 {
|
|
compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
|
|
reg = <0 0xe6e88000 0 0x1000>;
|
|
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
|
|
<&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
|
|
clock-names = "clkp1", "clkp2", "can_clk";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
status = "disabled";
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
/* External root clock */
|
|
extal_clk: extal {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overriden by the board. */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
/* External USB clock - can be overridden by the board */
|
|
usb_extal_clk: usb_extal {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
/* External CAN clock */
|
|
can_clk: can {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overridden by the board. */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
/* External SCIF clock */
|
|
scif_clk: scif {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overridden by the board. */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
/*
|
|
* The external audio clocks are configured as 0 Hz fixed
|
|
* frequency clocks by default. Boards that provide audio
|
|
* clocks should override them.
|
|
*/
|
|
audio_clka: audio_clka {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
audio_clkb: audio_clkb {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
audio_clkc: audio_clkc {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
/* Special CPG clocks */
|
|
cpg_clocks: cpg_clocks@e6150000 {
|
|
compatible = "renesas,r8a7794-cpg-clocks",
|
|
"renesas,rcar-gen2-cpg-clocks";
|
|
reg = <0 0xe6150000 0 0x1000>;
|
|
clocks = <&extal_clk &usb_extal_clk>;
|
|
#clock-cells = <1>;
|
|
clock-output-names = "main", "pll0", "pll1", "pll3",
|
|
"lb", "qspi", "sdh", "sd0", "rcan";
|
|
#power-domain-cells = <0>;
|
|
};
|
|
/* Variable factor clocks */
|
|
sd2_clk: sd2@e6150078 {
|
|
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe6150078 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
};
|
|
sd3_clk: sd3@e615026c {
|
|
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe615026c 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
};
|
|
mmc0_clk: mmc0@e6150240 {
|
|
compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe6150240 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
/* Fixed factor clocks */
|
|
pll1_div2_clk: pll1_div2 {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
};
|
|
z2_clk: z2 {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL0>;
|
|
#clock-cells = <0>;
|
|
clock-div = <1>;
|
|
clock-mult = <1>;
|
|
};
|
|
zg_clk: zg {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <6>;
|
|
clock-mult = <1>;
|
|
};
|
|
zx_clk: zx {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <3>;
|
|
clock-mult = <1>;
|
|
};
|
|
zs_clk: zs {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <6>;
|
|
clock-mult = <1>;
|
|
};
|
|
hp_clk: hp {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <12>;
|
|
clock-mult = <1>;
|
|
};
|
|
i_clk: i {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
};
|
|
b_clk: b {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <12>;
|
|
clock-mult = <1>;
|
|
};
|
|
p_clk: p {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <24>;
|
|
clock-mult = <1>;
|
|
};
|
|
cl_clk: cl {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <48>;
|
|
clock-mult = <1>;
|
|
};
|
|
m2_clk: m2 {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
};
|
|
rclk_clk: rclk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <(48 * 1024)>;
|
|
clock-mult = <1>;
|
|
};
|
|
oscclk_clk: oscclk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <(12 * 1024)>;
|
|
clock-mult = <1>;
|
|
};
|
|
zb3_clk: zb3 {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
|
|
#clock-cells = <0>;
|
|
clock-div = <4>;
|
|
clock-mult = <1>;
|
|
};
|
|
zb3d2_clk: zb3d2 {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
};
|
|
ddr_clk: ddr {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
};
|
|
mp_clk: mp {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-div = <15>;
|
|
clock-mult = <1>;
|
|
};
|
|
cp_clk: cp {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <48>;
|
|
clock-mult = <1>;
|
|
};
|
|
|
|
acp_clk: acp {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&extal_clk>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
};
|
|
|
|
/* Gate clocks */
|
|
mstp0_clks: mstp0_clks@e6150130 {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
|
|
clocks = <&mp_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <R8A7794_CLK_MSIOF0>;
|
|
clock-output-names = "msiof0";
|
|
};
|
|
mstp1_clks: mstp1_clks@e6150134 {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
|
|
clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
|
|
<&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
|
|
<&zs_clk>, <&zs_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
|
|
R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
|
|
R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
|
|
R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
|
|
>;
|
|
clock-output-names =
|
|
"vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
|
|
"tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
|
|
};
|
|
mstp2_clks: mstp2_clks@e6150138 {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
|
|
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
|
|
<&mp_clk>, <&mp_clk>, <&mp_clk>,
|
|
<&zs_clk>, <&zs_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
|
|
R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
|
|
R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
|
|
R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
|
|
>;
|
|
clock-output-names =
|
|
"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
|
|
"scifb1", "msiof1", "scifb2",
|
|
"sys-dmac1", "sys-dmac0";
|
|
};
|
|
mstp3_clks: mstp3_clks@e615013c {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
|
clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
|
|
<&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
|
|
<&hp_clk>, <&hp_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
|
|
R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
|
|
R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
|
|
R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
|
|
>;
|
|
clock-output-names =
|
|
"sdhi2", "sdhi1", "sdhi0",
|
|
"mmcif0", "i2c6", "i2c7",
|
|
"cmt1", "usbdmac0", "usbdmac1";
|
|
};
|
|
mstp4_clks: mstp4_clks@e6150140 {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
|
|
clocks = <&cp_clk>, <&zs_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <R8A7794_CLK_IRQC R8A7794_CLK_INTC_SYS>;
|
|
clock-output-names = "irqc", "intc-sys";
|
|
};
|
|
mstp5_clks: mstp5_clks@e6150144 {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
|
|
clocks = <&hp_clk>, <&p_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <R8A7794_CLK_AUDIO_DMAC0
|
|
R8A7794_CLK_PWM>;
|
|
clock-output-names = "audmac0", "pwm";
|
|
};
|
|
mstp7_clks: mstp7_clks@e615014c {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
|
|
clocks = <&mp_clk>, <&hp_clk>,
|
|
<&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
|
|
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
|
|
<&zx_clk>, <&zx_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
|
|
R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
|
|
R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
|
|
R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
|
|
R8A7794_CLK_SCIF0
|
|
R8A7794_CLK_DU1 R8A7794_CLK_DU0
|
|
>;
|
|
clock-output-names =
|
|
"ehci", "hsusb",
|
|
"hscif2", "scif5", "scif4", "hscif1", "hscif0",
|
|
"scif3", "scif2", "scif1", "scif0",
|
|
"du1", "du0";
|
|
};
|
|
mstp8_clks: mstp8_clks@e6150990 {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
|
|
clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
|
|
R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
|
|
>;
|
|
clock-output-names =
|
|
"vin1", "vin0", "etheravb", "ether";
|
|
};
|
|
mstp9_clks: mstp9_clks@e6150994 {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
|
|
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
|
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
|
|
<&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
|
|
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
|
|
<&hp_clk>, <&hp_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
|
|
R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
|
|
R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
|
|
R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
|
|
R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
|
|
R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
|
|
R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
|
|
R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
|
|
clock-output-names =
|
|
"gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
|
|
"gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
|
|
"i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
|
|
};
|
|
mstp10_clks: mstp10_clks@e6150998 {
|
|
compatible = "renesas,r8a7794-mstp-clocks",
|
|
"renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
|
|
clocks = <&p_clk>,
|
|
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
|
<&p_clk>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_ALL>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <R8A7794_CLK_SSI_ALL
|
|
R8A7794_CLK_SSI9 R8A7794_CLK_SSI8
|
|
R8A7794_CLK_SSI7 R8A7794_CLK_SSI6
|
|
R8A7794_CLK_SSI5 R8A7794_CLK_SSI4
|
|
R8A7794_CLK_SSI3 R8A7794_CLK_SSI2
|
|
R8A7794_CLK_SSI1 R8A7794_CLK_SSI0
|
|
R8A7794_CLK_SCU_ALL
|
|
R8A7794_CLK_SCU_DVC1
|
|
R8A7794_CLK_SCU_DVC0
|
|
R8A7794_CLK_SCU_CTU1_MIX1
|
|
R8A7794_CLK_SCU_CTU0_MIX0
|
|
R8A7794_CLK_SCU_SRC6
|
|
R8A7794_CLK_SCU_SRC5
|
|
R8A7794_CLK_SCU_SRC4
|
|
R8A7794_CLK_SCU_SRC3
|
|
R8A7794_CLK_SCU_SRC2
|
|
R8A7794_CLK_SCU_SRC1>;
|
|
clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7",
|
|
"ssi6", "ssi5", "ssi4", "ssi3",
|
|
"ssi2", "ssi1", "ssi0",
|
|
"scu-all", "scu-dvc1", "scu-dvc0",
|
|
"scu-ctu1-mix1", "scu-ctu0-mix0",
|
|
"scu-src6", "scu-src5", "scu-src4",
|
|
"scu-src3", "scu-src2", "scu-src1";
|
|
};
|
|
mstp11_clks: mstp11_clks@e615099c {
|
|
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
|
|
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
|
|
>;
|
|
clock-output-names = "scifa3", "scifa4", "scifa5";
|
|
};
|
|
};
|
|
|
|
rst: reset-controller@e6160000 {
|
|
compatible = "renesas,r8a7794-rst";
|
|
reg = <0 0xe6160000 0 0x0100>;
|
|
};
|
|
|
|
prr: chipid@ff000044 {
|
|
compatible = "renesas,prr";
|
|
reg = <0 0xff000044 0 4>;
|
|
};
|
|
|
|
sysc: system-controller@e6180000 {
|
|
compatible = "renesas,r8a7794-sysc";
|
|
reg = <0 0xe6180000 0 0x0200>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
ipmmu_sy0: mmu@e6280000 {
|
|
compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
|
|
reg = <0 0xe6280000 0 0x1000>;
|
|
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ipmmu_sy1: mmu@e6290000 {
|
|
compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
|
|
reg = <0 0xe6290000 0 0x1000>;
|
|
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ipmmu_ds: mmu@e6740000 {
|
|
compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
|
|
reg = <0 0xe6740000 0 0x1000>;
|
|
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ipmmu_mp: mmu@ec680000 {
|
|
compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
|
|
reg = <0 0xec680000 0 0x1000>;
|
|
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ipmmu_mx: mmu@fe951000 {
|
|
compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
|
|
reg = <0 0xfe951000 0 0x1000>;
|
|
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ipmmu_gp: mmu@e62a0000 {
|
|
compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
|
|
reg = <0 0xe62a0000 0 0x1000>;
|
|
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rcar_sound: sound@ec500000 {
|
|
/*
|
|
* #sound-dai-cells is required
|
|
*
|
|
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
|
|
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
|
|
*/
|
|
compatible = "renesas,rcar_sound-r8a7794",
|
|
"renesas,rcar_sound-gen2";
|
|
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
|
<0 0xec5a0000 0 0x100>, /* ADG */
|
|
<0 0xec540000 0 0x1000>, /* SSIU */
|
|
<0 0xec541000 0 0x280>, /* SSI */
|
|
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
|
|
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
|
|
|
clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>,
|
|
<&mstp10_clks R8A7794_CLK_SSI9>,
|
|
<&mstp10_clks R8A7794_CLK_SSI8>,
|
|
<&mstp10_clks R8A7794_CLK_SSI7>,
|
|
<&mstp10_clks R8A7794_CLK_SSI6>,
|
|
<&mstp10_clks R8A7794_CLK_SSI5>,
|
|
<&mstp10_clks R8A7794_CLK_SSI4>,
|
|
<&mstp10_clks R8A7794_CLK_SSI3>,
|
|
<&mstp10_clks R8A7794_CLK_SSI2>,
|
|
<&mstp10_clks R8A7794_CLK_SSI1>,
|
|
<&mstp10_clks R8A7794_CLK_SSI0>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_SRC6>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_SRC5>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_SRC4>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_SRC3>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_SRC2>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_SRC1>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_DVC0>,
|
|
<&mstp10_clks R8A7794_CLK_SCU_DVC1>,
|
|
<&audio_clka>, <&audio_clkb>, <&audio_clkc>,
|
|
<&m2_clk>;
|
|
clock-names = "ssi-all",
|
|
"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
|
|
"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
|
|
"src.6", "src.5", "src.4", "src.3", "src.2",
|
|
"src.1",
|
|
"ctu.0", "ctu.1",
|
|
"mix.0", "mix.1",
|
|
"dvc.0", "dvc.1",
|
|
"clk_a", "clk_b", "clk_c", "clk_i";
|
|
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
|
|
|
|
status = "disabled";
|
|
|
|
rcar_sound,dvc {
|
|
dvc0: dvc-0 {
|
|
dmas = <&audma0 0xbc>;
|
|
dma-names = "tx";
|
|
};
|
|
dvc1: dvc-1 {
|
|
dmas = <&audma0 0xbe>;
|
|
dma-names = "tx";
|
|
};
|
|
};
|
|
|
|
rcar_sound,mix {
|
|
mix0: mix-0 { };
|
|
mix1: mix-1 { };
|
|
};
|
|
|
|
rcar_sound,ctu {
|
|
ctu00: ctu-0 { };
|
|
ctu01: ctu-1 { };
|
|
ctu02: ctu-2 { };
|
|
ctu03: ctu-3 { };
|
|
ctu10: ctu-4 { };
|
|
ctu11: ctu-5 { };
|
|
ctu12: ctu-6 { };
|
|
ctu13: ctu-7 { };
|
|
};
|
|
|
|
rcar_sound,src {
|
|
src-0 {
|
|
status = "disabled";
|
|
};
|
|
src1: src-1 {
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x87>, <&audma0 0x9c>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src2: src-2 {
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x89>, <&audma0 0x9e>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src3: src-3 {
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x8b>, <&audma0 0xa0>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src4: src-4 {
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x8d>, <&audma0 0xb0>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src5: src-5 {
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x8f>, <&audma0 0xb2>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src6: src-6 {
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x91>, <&audma0 0xb4>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
};
|
|
|
|
rcar_sound,ssi {
|
|
ssi0: ssi-0 {
|
|
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x01>, <&audma0 0x02>,
|
|
<&audma0 0x15>, <&audma0 0x16>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi1: ssi-1 {
|
|
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x03>, <&audma0 0x04>,
|
|
<&audma0 0x49>, <&audma0 0x4a>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi2: ssi-2 {
|
|
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x05>, <&audma0 0x06>,
|
|
<&audma0 0x63>, <&audma0 0x64>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi3: ssi-3 {
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x07>, <&audma0 0x08>,
|
|
<&audma0 0x6f>, <&audma0 0x70>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi4: ssi-4 {
|
|
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x09>, <&audma0 0x0a>,
|
|
<&audma0 0x71>, <&audma0 0x72>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi5: ssi-5 {
|
|
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x0b>, <&audma0 0x0c>,
|
|
<&audma0 0x73>, <&audma0 0x74>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi6: ssi-6 {
|
|
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x0d>, <&audma0 0x0e>,
|
|
<&audma0 0x75>, <&audma0 0x76>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi7: ssi-7 {
|
|
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x0f>, <&audma0 0x10>,
|
|
<&audma0 0x79>, <&audma0 0x7a>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi8: ssi-8 {
|
|
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x11>, <&audma0 0x12>,
|
|
<&audma0 0x7b>, <&audma0 0x7c>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi9: ssi-9 {
|
|
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x13>, <&audma0 0x14>,
|
|
<&audma0 0x7d>, <&audma0 0x7e>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
};
|
|
};
|
|
};
|