Mike Turquette a854aea24c Adds support getting the divider registers for the MAIN PLL that was once ... thought to be hidden. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJTcQUFAAoJEBmUBAuBoyj0hFkP/2lSyq+o4swmhovXFV8xLlvg lgIq7m7RXqc8kSbz7RhbVOmjvTr7Kb5YRBQO7mIqJQpM/4lzUrsgGc9m7LZc6Rnh eP4Dt37gHCmacEwtjRp5nvQ5t0NaXXocctyb0LHKjuDRJlNkqd6Qcx+Lj4fXjsCf flWAxJN2ZG5BA8m5KCWPemYjiQblQUKNphphjte1AWgvl/yyzOSLneobnfdMFbiR jkaUBAw2vUYvz4NjJzw9f1aS8EUpc2IO6tLXERVZ7V6+rCakHK+DH1tzstlfqES0 zIdEzoV1PzBiIreptLGH9EbM8nmFIX/7whijtEvOoxkHeLPtTUnTm0Mv0KGVR5wF k3tMPeNP0BDNJ/69nPnxbr7dSw1xkLU9UavY+/t7Jq5fAt4/DsOoPxRnbxOQI+SM Lf3KS+j7nLQ7ueOgaB7tiDS5unNRqaY0ys0MggeA9xA544gcTf/2sg/qS9ur7PP5 jJ0yumtyunDCCI2xh0vUOipHNb0wbx9gCylgvPzatB8kDYaInOLA+ifVo9GJECd4 jdKoS848wBYZESSaiEGGL5VcLhKAhE4ycLpsWHh5wFScr+4KfBVr/vcm2cZs3XIG ISANaRoDFOtk8jCwNw2wTveW1tLsQHFU1ldoMfFcvKzESQkoe4PM+s4waRLduPLx 3OjACqD98ydI76tNli0f =anDE -----END PGP SIGNATURE----- Merge tag 'socfpga-clk-update-for-v3.16' of git://git.rocketboards.org/linux-socfpga-next into clk-next-socfpga Adds support getting the divider registers for the MAIN PLL that was once thought to be hidden.		2014-05-12 19:11:13 -07:00
..
clk-gate.c	clk: socfpga: add divider registers to the main pll outputs	2014-05-12 12:27:22 -05:00
clk-periph.c	clk: socfpga: add divider registers to the main pll outputs	2014-05-12 12:27:22 -05:00
clk-pll.c	clk: socfpga: fix clock driver for 3.15	2014-04-30 11:44:01 -07:00
clk.c	clk: socfpga: fix clock driver for 3.15	2014-04-30 11:44:01 -07:00
clk.h	clk: socfpga: add divider registers to the main pll outputs	2014-05-12 12:27:22 -05:00
Makefile	clk: socfpga: split clk code	2014-02-18 14:08:13 -08:00