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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c5379ba8fc
Until now, our understanding for HW I/O coherency to work on the Cortex-A9 based Marvell SoC was that only the PCIe regions should be mapped strongly-ordered. However, we were still encountering some deadlocks, especially when testing the CESA crypto engine. After checking with the HW designers, it was concluded that all the MMIO registers should be mapped as strongly ordered for the HW I/O coherency mechanism to work properly. This fixes some easy to reproduce deadlocks with the CESA crypto engine driver (dmcrypt on a sufficiently large disk partition). Tested-by: Terry Stockert <stockert@inkblotadmirer.me> Tested-by: Romain Perier <romain.perier@free-electrons.com> Cc: Terry Stockert <stockert@inkblotadmirer.me> Cc: Romain Perier <romain.perier@free-electrons.com> Cc: <stable@vger.kernel.org> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> |
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| .. | ||
| armada-370-xp.h | ||
| board-v7.c | ||
| coherency_ll.S | ||
| coherency.c | ||
| coherency.h | ||
| common.h | ||
| cpu-reset.c | ||
| dove.c | ||
| headsmp-a9.S | ||
| headsmp.S | ||
| Kconfig | ||
| kirkwood-pm.c | ||
| kirkwood-pm.h | ||
| kirkwood.c | ||
| kirkwood.h | ||
| Makefile | ||
| mvebu-soc-id.c | ||
| mvebu-soc-id.h | ||
| platsmp-a9.c | ||
| platsmp.c | ||
| pm-board.c | ||
| pm.c | ||
| pmsu_ll.S | ||
| pmsu.c | ||
| pmsu.h | ||
| system-controller.c | ||