mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 10:46:44 +07:00
41db12df64
Improve the readibility of the function which inserts command buffers and other maintanence commands into the GPUs ring buffer. We do this by splitting the ring buffer reservation in two: one chunk for any commands that need to be issued prior to the command buffer, and a separate chunk for commands issued after the buffer. The result is a much more obvious code flow in this function, and localisation of the conditional maintanence commands prior to the command buffer. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
328 lines
9.3 KiB
C
328 lines
9.3 KiB
C
/*
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* Copyright (C) 2014 Etnaviv Project
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* Author: Christian Gmeiner <christian.gmeiner@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "etnaviv_gpu.h"
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#include "etnaviv_gem.h"
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#include "etnaviv_mmu.h"
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#include "common.xml.h"
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#include "state.xml.h"
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#include "state_3d.xml.h"
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#include "cmdstream.xml.h"
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/*
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* Command Buffer helper:
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*/
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static inline void OUT(struct etnaviv_cmdbuf *buffer, u32 data)
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{
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u32 *vaddr = (u32 *)buffer->vaddr;
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BUG_ON(buffer->user_size >= buffer->size);
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vaddr[buffer->user_size / 4] = data;
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buffer->user_size += 4;
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}
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static inline void CMD_LOAD_STATE(struct etnaviv_cmdbuf *buffer,
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u32 reg, u32 value)
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{
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u32 index = reg >> VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR;
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buffer->user_size = ALIGN(buffer->user_size, 8);
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/* write a register via cmd stream */
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OUT(buffer, VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE |
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VIV_FE_LOAD_STATE_HEADER_COUNT(1) |
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VIV_FE_LOAD_STATE_HEADER_OFFSET(index));
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OUT(buffer, value);
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}
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static inline void CMD_END(struct etnaviv_cmdbuf *buffer)
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{
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buffer->user_size = ALIGN(buffer->user_size, 8);
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OUT(buffer, VIV_FE_END_HEADER_OP_END);
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}
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static inline void CMD_WAIT(struct etnaviv_cmdbuf *buffer)
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{
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buffer->user_size = ALIGN(buffer->user_size, 8);
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OUT(buffer, VIV_FE_WAIT_HEADER_OP_WAIT | 200);
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}
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static inline void CMD_LINK(struct etnaviv_cmdbuf *buffer,
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u16 prefetch, u32 address)
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{
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buffer->user_size = ALIGN(buffer->user_size, 8);
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OUT(buffer, VIV_FE_LINK_HEADER_OP_LINK |
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VIV_FE_LINK_HEADER_PREFETCH(prefetch));
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OUT(buffer, address);
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}
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static inline void CMD_STALL(struct etnaviv_cmdbuf *buffer,
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u32 from, u32 to)
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{
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buffer->user_size = ALIGN(buffer->user_size, 8);
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OUT(buffer, VIV_FE_STALL_HEADER_OP_STALL);
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OUT(buffer, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to));
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}
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static inline void CMD_SEM(struct etnaviv_cmdbuf *buffer, u32 from, u32 to)
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{
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CMD_LOAD_STATE(buffer, VIVS_GL_SEMAPHORE_TOKEN,
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VIVS_GL_SEMAPHORE_TOKEN_FROM(from) |
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VIVS_GL_SEMAPHORE_TOKEN_TO(to));
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}
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static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu,
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struct etnaviv_cmdbuf *buffer, u8 pipe)
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{
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u32 flush = 0;
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/*
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* This assumes that if we're switching to 2D, we're switching
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* away from 3D, and vice versa. Hence, if we're switching to
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* the 2D core, we need to flush the 3D depth and color caches,
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* otherwise we need to flush the 2D pixel engine cache.
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*/
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if (gpu->exec_state == ETNA_PIPE_2D)
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flush = VIVS_GL_FLUSH_CACHE_PE2D;
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else if (gpu->exec_state == ETNA_PIPE_3D)
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flush = VIVS_GL_FLUSH_CACHE_DEPTH | VIVS_GL_FLUSH_CACHE_COLOR;
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CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
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CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_LOAD_STATE(buffer, VIVS_GL_PIPE_SELECT,
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VIVS_GL_PIPE_SELECT_PIPE(pipe));
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}
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static u32 gpu_va(struct etnaviv_gpu *gpu, struct etnaviv_cmdbuf *buf)
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{
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return buf->paddr - gpu->memory_base;
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}
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static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu,
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struct etnaviv_cmdbuf *buf, u32 off, u32 len)
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{
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u32 size = buf->size;
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u32 *ptr = buf->vaddr + off;
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dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n",
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ptr, gpu_va(gpu, buf) + off, size - len * 4 - off);
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print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
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ptr, len * 4, 0);
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}
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/*
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* Safely replace the WAIT of a waitlink with a new command and argument.
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* The GPU may be executing this WAIT while we're modifying it, so we have
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* to write it in a specific order to avoid the GPU branching to somewhere
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* else. 'wl_offset' is the offset to the first byte of the WAIT command.
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*/
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static void etnaviv_buffer_replace_wait(struct etnaviv_cmdbuf *buffer,
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unsigned int wl_offset, u32 cmd, u32 arg)
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{
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u32 *lw = buffer->vaddr + wl_offset;
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lw[1] = arg;
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mb();
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lw[0] = cmd;
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mb();
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}
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/*
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* Ensure that there is space in the command buffer to contiguously write
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* 'cmd_dwords' 64-bit words into the buffer, wrapping if necessary.
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*/
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static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu,
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struct etnaviv_cmdbuf *buffer, unsigned int cmd_dwords)
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{
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if (buffer->user_size + cmd_dwords * sizeof(u64) > buffer->size)
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buffer->user_size = 0;
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return gpu_va(gpu, buffer) + buffer->user_size;
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}
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u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_cmdbuf *buffer = gpu->buffer;
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/* initialize buffer */
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buffer->user_size = 0;
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CMD_WAIT(buffer);
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CMD_LINK(buffer, 2, gpu_va(gpu, buffer) + buffer->user_size - 4);
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return buffer->user_size / 8;
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}
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void etnaviv_buffer_end(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_cmdbuf *buffer = gpu->buffer;
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unsigned int waitlink_offset = buffer->user_size - 16;
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u32 link_target, flush = 0;
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if (gpu->exec_state == ETNA_PIPE_2D)
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flush = VIVS_GL_FLUSH_CACHE_PE2D;
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else if (gpu->exec_state == ETNA_PIPE_3D)
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flush = VIVS_GL_FLUSH_CACHE_DEPTH |
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VIVS_GL_FLUSH_CACHE_COLOR |
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VIVS_GL_FLUSH_CACHE_TEXTURE |
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VIVS_GL_FLUSH_CACHE_TEXTUREVS |
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VIVS_GL_FLUSH_CACHE_SHADER_L2;
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if (flush) {
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unsigned int dwords = 7;
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link_target = etnaviv_buffer_reserve(gpu, buffer, dwords);
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CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
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if (gpu->exec_state == ETNA_PIPE_3D)
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CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,
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VIVS_TS_FLUSH_CACHE_FLUSH);
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CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_END(buffer);
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etnaviv_buffer_replace_wait(buffer, waitlink_offset,
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VIV_FE_LINK_HEADER_OP_LINK |
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VIV_FE_LINK_HEADER_PREFETCH(dwords),
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link_target);
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} else {
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/* Replace the last link-wait with an "END" command */
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etnaviv_buffer_replace_wait(buffer, waitlink_offset,
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VIV_FE_END_HEADER_OP_END, 0);
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}
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}
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/* Append a command buffer to the ring buffer. */
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void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event,
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struct etnaviv_cmdbuf *cmdbuf)
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{
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struct etnaviv_cmdbuf *buffer = gpu->buffer;
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unsigned int waitlink_offset = buffer->user_size - 16;
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u32 return_target, return_dwords;
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u32 link_target, link_dwords;
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if (drm_debug & DRM_UT_DRIVER)
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etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
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link_target = gpu_va(gpu, cmdbuf);
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link_dwords = cmdbuf->size / 8;
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/*
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* If we need maintanence prior to submitting this buffer, we will
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* need to append a mmu flush load state, followed by a new
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* link to this buffer - a total of four additional words.
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*/
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if (gpu->mmu->need_flush || gpu->switch_context) {
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u32 target, extra_dwords;
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/* link command */
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extra_dwords = 1;
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/* flush command */
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if (gpu->mmu->need_flush)
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extra_dwords += 1;
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/* pipe switch commands */
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if (gpu->switch_context)
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extra_dwords += 4;
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target = etnaviv_buffer_reserve(gpu, buffer, extra_dwords);
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if (gpu->mmu->need_flush) {
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/* Add the MMU flush */
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CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,
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VIVS_GL_FLUSH_MMU_FLUSH_FEMMU |
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VIVS_GL_FLUSH_MMU_FLUSH_UNK1 |
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VIVS_GL_FLUSH_MMU_FLUSH_UNK2 |
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VIVS_GL_FLUSH_MMU_FLUSH_PEMMU |
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VIVS_GL_FLUSH_MMU_FLUSH_UNK4);
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gpu->mmu->need_flush = false;
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}
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if (gpu->switch_context) {
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etnaviv_cmd_select_pipe(gpu, buffer, cmdbuf->exec_state);
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gpu->exec_state = cmdbuf->exec_state;
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gpu->switch_context = false;
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}
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/* And the link to the submitted buffer */
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CMD_LINK(buffer, link_dwords, link_target);
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/* Update the link target to point to above instructions */
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link_target = target;
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link_dwords = extra_dwords;
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}
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/*
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* Append a LINK to the submitted command buffer to return to
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* the ring buffer. return_target is the ring target address.
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* We need three dwords: event, wait, link.
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*/
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return_dwords = 3;
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return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords);
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CMD_LINK(cmdbuf, return_dwords, return_target);
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/*
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* Append event, wait and link pointing back to the wait
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* command to the ring buffer.
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*/
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CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |
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VIVS_GL_EVENT_FROM_PE);
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CMD_WAIT(buffer);
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CMD_LINK(buffer, 2, return_target + 8);
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if (drm_debug & DRM_UT_DRIVER)
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pr_info("stream link to 0x%08x @ 0x%08x %p\n",
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return_target, gpu_va(gpu, cmdbuf), cmdbuf->vaddr);
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if (drm_debug & DRM_UT_DRIVER) {
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print_hex_dump(KERN_INFO, "cmd ", DUMP_PREFIX_OFFSET, 16, 4,
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cmdbuf->vaddr, cmdbuf->size, 0);
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pr_info("link op: %p\n", buffer->vaddr + waitlink_offset);
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pr_info("addr: 0x%08x\n", link_target);
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pr_info("back: 0x%08x\n", return_target);
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pr_info("event: %d\n", event);
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}
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/*
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* Kick off the submitted command by replacing the previous
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* WAIT with a link to the address in the ring buffer.
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*/
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etnaviv_buffer_replace_wait(buffer, waitlink_offset,
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VIV_FE_LINK_HEADER_OP_LINK |
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VIV_FE_LINK_HEADER_PREFETCH(link_dwords),
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link_target);
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if (drm_debug & DRM_UT_DRIVER)
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etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
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}
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