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a87af2db72
This augments the platform bindings for the Gemini SoC to include the fact that the system controller also provides clock and reset lines. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
109 lines
3.4 KiB
Plaintext
109 lines
3.4 KiB
Plaintext
Cortina systems Gemini platforms
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The Gemini SoC is the project name for an ARMv4 FA525-based SoC originally
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produced by Storlink Semiconductor around 2005. The company was renamed
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later renamed Storm Semiconductor. The chip product name is Storlink SL3516.
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It was derived from earlier products from Storm named SL3316 (Centroid) and
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SL3512 (Bulverde).
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Storm Semiconductor was acquired by Cortina Systems in 2008 and the SoC was
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produced and used for NAS and similar usecases. In 2014 Cortina Systems was
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in turn acquired by Inphi, who seem to have discontinued this product family.
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Many of the IP blocks used in the SoC comes from Faraday Technology.
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Required properties (in root node):
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compatible = "cortina,gemini";
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Required nodes:
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- soc: the SoC should be represented by a simple bus encompassing all the
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onchip devices, this is referred to as the soc bus node.
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- syscon: the soc bus node must have a system controller node pointing to the
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global control registers, with the compatible string
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"cortina,gemini-syscon", "syscon";
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Required properties on the syscon:
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- reg: syscon register location and size.
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- #clock-cells: should be set to <1> - the system controller is also a
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clock provider.
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- #reset-cells: should be set to <1> - the system controller is also a
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reset line provider.
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The clock sources have shorthand defines in the include file:
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<dt-bindings/clock/cortina,gemini-clock.h>
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The reset lines have shorthand defines in the include file:
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<dt-bindings/reset/cortina,gemini-reset.h>
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- timer: the soc bus node must have a timer node pointing to the SoC timer
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block, with the compatible string "cortina,gemini-timer"
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See: clocksource/cortina,gemini-timer.txt
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- interrupt-controller: the sob bus node must have an interrupt controller
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node pointing to the SoC interrupt controller block, with the compatible
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string "cortina,gemini-interrupt-controller"
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See interrupt-controller/cortina,gemini-interrupt-controller.txt
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Example:
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/ {
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model = "Foo Gemini Machine";
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compatible = "cortina,gemini";
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#address-cells = <1>;
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#size-cells = <1>;
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memory {
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device_type = "memory";
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reg = <0x00000000 0x8000000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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interrupt-parent = <&intcon>;
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syscon: syscon@40000000 {
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compatible = "cortina,gemini-syscon", "syscon";
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reg = <0x40000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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uart0: serial@42000000 {
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compatible = "ns16550a";
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reg = <0x42000000 0x100>;
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resets = <&syscon GEMINI_RESET_UART>;
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clocks = <&syscon GEMINI_CLK_UART>;
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interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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};
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timer@43000000 {
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compatible = "cortina,gemini-timer";
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reg = <0x43000000 0x1000>;
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interrupt-parent = <&intcon>;
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interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
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<15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
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<16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
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resets = <&syscon GEMINI_RESET_TIMER>;
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/* APB clock or RTC clock */
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clocks = <&syscon GEMINI_CLK_APB>,
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<&syscon GEMINI_CLK_RTC>;
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clock-names = "PCLK", "EXTCLK";
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syscon = <&syscon>;
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};
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intcon: interrupt-controller@48000000 {
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compatible = "cortina,gemini-interrupt-controller";
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reg = <0x48000000 0x1000>;
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resets = <&syscon GEMINI_RESET_INTCON0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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};
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