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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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efb45b305f
This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
172 lines
3.0 KiB
Plaintext
172 lines
3.0 KiB
Plaintext
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "skeleton.dtsi"
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#include "vfxxx.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a5_cpu: cpu@0 {
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compatible = "arm,cortex-a5";
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device_type = "cpu";
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reg = <0x0>;
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};
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};
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soc {
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interrupt-parent = <&intc>;
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aips-bus@40000000 {
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intc: interrupt-controller@40002000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x40003000 0x1000>,
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<0x40002100 0x100>;
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};
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global_timer: timer@40002200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x40002200 0x20>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks VF610_CLK_PLATFORM_BUS>;
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};
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};
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};
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};
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&adc0 {
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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};
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&adc1 {
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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};
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&can0 {
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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};
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&can1 {
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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};
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&dspi0 {
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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};
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&edma0 {
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma-tx", "edma-err";
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};
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&edma1 {
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma-tx", "edma-err";
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};
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&esdhc1 {
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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};
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&fec0 {
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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};
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&fec1 {
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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};
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&ftm {
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio1 {
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio2 {
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio3 {
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio4 {
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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};
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&gpio5 {
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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};
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&i2c0 {
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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};
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&pit {
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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};
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&qspi0 {
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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};
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&sai2 {
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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};
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&uart0 {
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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};
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&uart1 {
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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};
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&uart2 {
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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};
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&uart3 {
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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};
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&uart4 {
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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};
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&uart5 {
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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};
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&usbdev0 {
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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};
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&usbh1 {
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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};
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&usbphy0 {
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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};
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&usbphy1 {
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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};
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