mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 19:41:34 +07:00
0c4b0f815f
- Fix microMIPS build failures by adding a .insn directive to the
barrier_before_unreachable() asm statement in order to convince the
toolchain that the asm statement is a valid branch target rather
than a bogus attempt to switch ISA.
- Clean up our declarations of TLB functions that we overwrite with
generated code in order to prevent the compiler making assumptions
about alignment that cause microMIPS kernels built with GCC 7 &
above to die early during boot.
- Fix up a regression for MIPS32 kernels which slipped into the main
MIPS pull for 4.19, causing CONFIG_32BIT=y kernels to contain
inappropriate MIPS64 instructions.
- Extend our existing workaround for MIPSr6 builds that end up using
the __multi3 intrinsic to GCC 7 & below, rather than just GCC 7.
-----BEGIN PGP SIGNATURE-----
iIsEABYIADMWIQRgLjeFAZEXQzy86/s+p5+stXUA3QUCW37wVhUccGF1bC5idXJ0
b25AbWlwcy5jb20ACgkQPqefrLV1AN18iAD/ZO02rgkTgMG7NvZMtbOwflxe1aVz
YpAQzcOSz+CBxgUA/30ZwZm37hgMi3YWOJMSfmbuWKsYi+/vkcjwlfai7UUF
=oJFy
-----END PGP SIGNATURE-----
Merge tag 'mips_4.19_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS fixes from Paul Burton:
- Fix microMIPS build failures by adding a .insn directive to the
barrier_before_unreachable() asm statement in order to convince the
toolchain that the asm statement is a valid branch target rather
than a bogus attempt to switch ISA.
- Clean up our declarations of TLB functions that we overwrite with
generated code in order to prevent the compiler making assumptions
about alignment that cause microMIPS kernels built with GCC 7 &
above to die early during boot.
- Fix up a regression for MIPS32 kernels which slipped into the main
MIPS pull for 4.19, causing CONFIG_32BIT=y kernels to contain
inappropriate MIPS64 instructions.
- Extend our existing workaround for MIPSr6 builds that end up using
the __multi3 intrinsic to GCC 7 & below, rather than just GCC 7.
* tag 'mips_4.19_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
MIPS: lib: Provide MIPS64r6 __multi3() for GCC < 7
MIPS: Workaround GCC __builtin_unreachable reordering bug
compiler.h: Allow arch-specific asm/compiler.h
MIPS: Avoid move psuedo-instruction whilst using MIPS_ISA_LEVEL
MIPS: Consistently declare TLB functions
MIPS: Export tlbmiss_handler_setup_pgd near its definition
426 lines
12 KiB
C
426 lines
12 KiB
C
/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*
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* But use these as seldom as possible since they are much more slower
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* than regular operations.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
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*/
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#ifndef _ASM_ATOMIC_H
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#define _ASM_ATOMIC_H
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#include <linux/irqflags.h>
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#include <linux/types.h>
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#include <asm/barrier.h>
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#include <asm/compiler.h>
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#include <asm/cpu-features.h>
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#include <asm/cmpxchg.h>
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#include <asm/war.h>
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/*
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* Using a branch-likely instruction to check the result of an sc instruction
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* works around a bug present in R10000 CPUs prior to revision 3.0 that could
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* cause ll-sc sequences to execute non-atomically.
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*/
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#if R10000_LLSC_WAR
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# define __scbeqz "beqzl"
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#else
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# define __scbeqz "beqz"
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#endif
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#define ATOMIC_INIT(i) { (i) }
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/*
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* atomic_read - read atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically reads the value of @v.
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*/
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#define atomic_read(v) READ_ONCE((v)->counter)
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/*
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* atomic_set - set atomic variable
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* @v: pointer of type atomic_t
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* @i: required value
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*
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* Atomically sets the value of @v to @i.
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*/
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#define atomic_set(v, i) WRITE_ONCE((v)->counter, (i))
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#define ATOMIC_OP(op, c_op, asm_op) \
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static __inline__ void atomic_##op(int i, atomic_t * v) \
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{ \
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if (kernel_uses_llsc) { \
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int temp; \
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\
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: ll %0, %1 # atomic_" #op " \n" \
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" " #asm_op " %0, %2 \n" \
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" sc %0, %1 \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" .set mips0 \n" \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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} \
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}
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static __inline__ int atomic_##op##_return_relaxed(int i, atomic_t * v) \
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{ \
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int result; \
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\
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if (kernel_uses_llsc) { \
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int temp; \
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\
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: ll %1, %2 # atomic_" #op "_return \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" sc %0, %2 \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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result = v->counter; \
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result c_op i; \
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v->counter = result; \
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raw_local_irq_restore(flags); \
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} \
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\
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return result; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \
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{ \
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int result; \
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\
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if (kernel_uses_llsc) { \
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int temp; \
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\
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: ll %1, %2 # atomic_fetch_" #op " \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" sc %0, %2 \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" .set mips0 \n" \
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" move %0, %1 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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result = v->counter; \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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} \
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\
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return result; \
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}
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_OP_RETURN(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(add, +=, addu)
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ATOMIC_OPS(sub, -=, subu)
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#define atomic_add_return_relaxed atomic_add_return_relaxed
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#define atomic_sub_return_relaxed atomic_sub_return_relaxed
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#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
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#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(and, &=, and)
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ATOMIC_OPS(or, |=, or)
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ATOMIC_OPS(xor, ^=, xor)
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#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed
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#define atomic_fetch_or_relaxed atomic_fetch_or_relaxed
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#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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/*
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* atomic_sub_if_positive - conditionally subtract integer from atomic variable
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* @i: integer value to subtract
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* @v: pointer of type atomic_t
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*
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* Atomically test @v and subtract @i if @v is greater or equal than @i.
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* The function returns the old value of @v minus @i.
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*/
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static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
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{
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int result;
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smp_mb__before_llsc();
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if (kernel_uses_llsc) {
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int temp;
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__asm__ __volatile__(
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" .set "MIPS_ISA_LEVEL" \n"
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"1: ll %1, %2 # atomic_sub_if_positive\n"
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" .set mips0 \n"
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" subu %0, %1, %3 \n"
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" move %1, %0 \n"
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" bltz %0, 1f \n"
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" .set "MIPS_ISA_LEVEL" \n"
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" sc %1, %2 \n"
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"\t" __scbeqz " %1, 1b \n"
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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"+" GCC_OFF_SMALL_ASM() (v->counter)
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: "Ir" (i));
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} else {
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unsigned long flags;
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raw_local_irq_save(flags);
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result = v->counter;
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result -= i;
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if (result >= 0)
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v->counter = result;
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raw_local_irq_restore(flags);
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}
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smp_llsc_mb();
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return result;
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}
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#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
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#define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
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/*
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* atomic_dec_if_positive - decrement by 1 if old value positive
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* @v: pointer of type atomic_t
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*/
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#define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v)
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#ifdef CONFIG_64BIT
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#define ATOMIC64_INIT(i) { (i) }
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/*
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* atomic64_read - read atomic variable
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* @v: pointer of type atomic64_t
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*
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*/
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#define atomic64_read(v) READ_ONCE((v)->counter)
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/*
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* atomic64_set - set atomic variable
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* @v: pointer of type atomic64_t
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* @i: required value
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*/
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#define atomic64_set(v, i) WRITE_ONCE((v)->counter, (i))
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#define ATOMIC64_OP(op, c_op, asm_op) \
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static __inline__ void atomic64_##op(long i, atomic64_t * v) \
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{ \
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if (kernel_uses_llsc) { \
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long temp; \
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\
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: lld %0, %1 # atomic64_" #op " \n" \
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" " #asm_op " %0, %2 \n" \
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" scd %0, %1 \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" .set mips0 \n" \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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} \
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}
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#define ATOMIC64_OP_RETURN(op, c_op, asm_op) \
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static __inline__ long atomic64_##op##_return_relaxed(long i, atomic64_t * v) \
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{ \
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long result; \
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\
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if (kernel_uses_llsc) { \
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long temp; \
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\
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: lld %1, %2 # atomic64_" #op "_return\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" scd %0, %2 \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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result = v->counter; \
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result c_op i; \
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v->counter = result; \
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raw_local_irq_restore(flags); \
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} \
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\
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return result; \
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}
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#define ATOMIC64_FETCH_OP(op, c_op, asm_op) \
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static __inline__ long atomic64_fetch_##op##_relaxed(long i, atomic64_t * v) \
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{ \
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long result; \
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\
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if (kernel_uses_llsc && R10000_LLSC_WAR) { \
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long temp; \
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\
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: lld %1, %2 # atomic64_fetch_" #op "\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" scd %0, %2 \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" move %0, %1 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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result = v->counter; \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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} \
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\
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return result; \
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}
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#define ATOMIC64_OPS(op, c_op, asm_op) \
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ATOMIC64_OP(op, c_op, asm_op) \
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ATOMIC64_OP_RETURN(op, c_op, asm_op) \
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ATOMIC64_FETCH_OP(op, c_op, asm_op)
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ATOMIC64_OPS(add, +=, daddu)
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ATOMIC64_OPS(sub, -=, dsubu)
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#define atomic64_add_return_relaxed atomic64_add_return_relaxed
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#define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
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#define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
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#define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
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#undef ATOMIC64_OPS
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#define ATOMIC64_OPS(op, c_op, asm_op) \
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ATOMIC64_OP(op, c_op, asm_op) \
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ATOMIC64_FETCH_OP(op, c_op, asm_op)
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ATOMIC64_OPS(and, &=, and)
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ATOMIC64_OPS(or, |=, or)
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ATOMIC64_OPS(xor, ^=, xor)
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#define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
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#define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed
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#define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
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#undef ATOMIC64_OPS
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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/*
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* atomic64_sub_if_positive - conditionally subtract integer from atomic
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* variable
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* @i: integer value to subtract
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* @v: pointer of type atomic64_t
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*
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* Atomically test @v and subtract @i if @v is greater or equal than @i.
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* The function returns the old value of @v minus @i.
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*/
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static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
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{
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long result;
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smp_mb__before_llsc();
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if (kernel_uses_llsc) {
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long temp;
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__asm__ __volatile__(
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" .set "MIPS_ISA_LEVEL" \n"
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"1: lld %1, %2 # atomic64_sub_if_positive\n"
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" dsubu %0, %1, %3 \n"
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" move %1, %0 \n"
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" bltz %0, 1f \n"
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" scd %1, %2 \n"
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"\t" __scbeqz " %1, 1b \n"
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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"+" GCC_OFF_SMALL_ASM() (v->counter)
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: "Ir" (i));
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} else {
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unsigned long flags;
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raw_local_irq_save(flags);
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result = v->counter;
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result -= i;
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if (result >= 0)
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v->counter = result;
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raw_local_irq_restore(flags);
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}
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smp_llsc_mb();
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return result;
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}
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#define atomic64_cmpxchg(v, o, n) \
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((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
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#define atomic64_xchg(v, new) (xchg(&((v)->counter), (new)))
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/*
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* atomic64_dec_if_positive - decrement by 1 if old value positive
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* @v: pointer of type atomic64_t
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*/
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#define atomic64_dec_if_positive(v) atomic64_sub_if_positive(1, v)
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#endif /* CONFIG_64BIT */
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#endif /* _ASM_ATOMIC_H */
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