mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 03:46:47 +07:00
610ac9381e
The clock support code for ColdFire CPUs currently supports those that have the clock control register PPMCR. Expose the struct clk for all CPU types and add a definition for all other ColdFire CPU types. With this we will be able to define simple clock trees for all ColdFire CPU types, even though they will not be able to be enabled or disabled. They will be able to report the clock rate. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
51 lines
997 B
C
51 lines
997 B
C
/*
|
|
* mcfclk.h -- coldfire specific clock structure
|
|
*/
|
|
|
|
|
|
#ifndef mcfclk_h
|
|
#define mcfclk_h
|
|
|
|
struct clk;
|
|
|
|
struct clk_ops {
|
|
void (*enable)(struct clk *);
|
|
void (*disable)(struct clk *);
|
|
};
|
|
|
|
struct clk {
|
|
const char *name;
|
|
struct clk_ops *clk_ops;
|
|
unsigned long rate;
|
|
unsigned long enabled;
|
|
u8 slot;
|
|
};
|
|
|
|
extern struct clk *mcf_clks[];
|
|
|
|
#ifdef MCFPM_PPMCR0
|
|
extern struct clk_ops clk_ops0;
|
|
#ifdef MCFPM_PPMCR1
|
|
extern struct clk_ops clk_ops1;
|
|
#endif /* MCFPM_PPMCR1 */
|
|
|
|
#define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
|
|
static struct clk __clk_##clk_bank##_##clk_slot = { \
|
|
.name = clk_name, \
|
|
.clk_ops = &clk_ops##clk_bank, \
|
|
.rate = clk_rate, \
|
|
.slot = clk_slot, \
|
|
}
|
|
|
|
void __clk_init_enabled(struct clk *);
|
|
void __clk_init_disabled(struct clk *);
|
|
#else
|
|
#define DEFINE_CLK(clk_ref, clk_name, clk_rate) \
|
|
static struct clk clk_##clk_ref = { \
|
|
.name = clk_name, \
|
|
.rate = clk_rate, \
|
|
}
|
|
#endif /* MCFPM_PPMCR0 */
|
|
|
|
#endif /* mcfclk_h */
|