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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c4755fb906
The display architecture has changed in several significant ways with the new Tegra186 SoC. Shared between all display controllers is a set of common resources referred to as the display hub. The hub generates accesses to memory and feeds them into various composition pipelines, each of which being a window that can be assigned to arbitrary heads. Atomic state is subclassed in order to track the global bandwidth requirements and select and adjust the hub clocks appropriately. The plane code is shared to a large degree with earlier SoC generations, except where the programming differs. Signed-off-by: Thierry Reding <treding@nvidia.com>
62 lines
1.3 KiB
C
62 lines
1.3 KiB
C
/*
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* Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef TEGRA_PLANE_H
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#define TEGRA_PLANE_H 1
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#include <drm/drm_plane.h>
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struct tegra_bo;
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struct tegra_plane {
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struct drm_plane base;
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unsigned int offset;
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unsigned int index;
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unsigned int depth;
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};
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struct tegra_cursor {
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struct tegra_plane base;
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struct tegra_bo *bo;
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unsigned int width;
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unsigned int height;
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};
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static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
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{
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return container_of(plane, struct tegra_plane, base);
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}
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struct tegra_plane_state {
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struct drm_plane_state base;
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struct tegra_bo_tiling tiling;
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u32 format;
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u32 swap;
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};
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static inline struct tegra_plane_state *
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to_tegra_plane_state(struct drm_plane_state *state)
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{
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if (state)
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return container_of(state, struct tegra_plane_state, base);
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return NULL;
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}
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extern const struct drm_plane_funcs tegra_plane_funcs;
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int tegra_plane_state_add(struct tegra_plane *plane,
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struct drm_plane_state *state);
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int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap);
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bool tegra_plane_format_is_yuv(unsigned int format, bool *planar);
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#endif /* TEGRA_PLANE_H */
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