Eric Yang c43f89f81c drm/amd/display: put back front end initialization sequence ... [Why] Seamless boot optimization removed proper front end power off sequence. In driver disable enable case, this causes driver to power gate hubp and dpp while there is still memory fetching going on, this can cause invalid memory requests to be generated which will hang data fabric. [How] Put back proper front end power off sequence Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-07-18 14:27:25 -05:00
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acp	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
amdgpu	drm/amdgpu: use VCN firmware offset for cache window	2019-07-18 14:18:07 -05:00
amdkfd	drm/amdkfd: Increase vcrat size for GPU	2019-07-18 14:18:07 -05:00
display	drm/amd/display: put back front end initialization sequence	2019-07-18 14:27:25 -05:00
include	drm/amdgpu: exposing fica registers to df offsets	2019-07-18 14:18:07 -05:00
powerplay	drm/amd/powerplay: change sysfs pp_dpm_xxx format for navi10	2019-07-18 14:18:07 -05:00