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93d39737b2
Broadcom SoC pins are controlled using CRU ("Clock and Reset Unit" or
"Central Resource Unit") registers. There are more CRU registers and
functions so CRU should be represented as a separated block in DT.
Moreover CRU is a sub-block of DMU ("Device Management Unit") so that
one should also get its own node.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
58 lines
1.5 KiB
Plaintext
58 lines
1.5 KiB
Plaintext
Broadcom Northstar pins mux controller
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Some of Northstar SoCs's pins can be used for various purposes thanks to the mux
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controller. This binding allows describing mux controller and listing available
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functions. They can be referenced later by other bindings to let system
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configure controller correctly.
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A list of pins varies across chipsets so few bindings are available.
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Required properties:
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- compatible: must be one of:
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"brcm,bcm4708-pinmux"
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"brcm,bcm4709-pinmux"
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"brcm,bcm53012-pinmux"
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- reg: iomem address range of CRU (Central Resource Unit) pin registers
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- reg-names: "cru_gpio_control" - the only needed & supported reg right now
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Functions and their groups available for all chipsets:
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- "spi": "spi_grp"
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- "i2c": "i2c_grp"
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- "pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"
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- "uart1": "uart1_grp"
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Additionally available on BCM4709 and BCM53012:
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- "mdio": "mdio_grp"
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- "uart2": "uart2_grp"
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- "sdio": "sdio_pwr_grp", "sdio_1p8v_grp"
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For documentation of subnodes see:
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Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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Example:
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dmu@1800c000 {
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compatible = "simple-bus";
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ranges = <0 0x1800c000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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cru@100 {
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compatible = "simple-bus";
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reg = <0x100 0x1a4>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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pin-controller@1c0 {
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compatible = "brcm,bcm4708-pinmux";
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reg = <0x1c0 0x24>;
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reg-names = "cru_gpio_control";
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spi-pins {
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function = "spi";
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groups = "spi_grp";
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};
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};
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};
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};
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