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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a85f06badc
The "pcie_xclk" clock is not actually a clock at all, but rather a reset domain. Now that the custom Tegra module reset API has been removed, we can remove the definition of any "clocks" that existed solely to support it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
274 lines
7.0 KiB
C
274 lines
7.0 KiB
C
/*
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* This header provides constants for binding nvidia,tegra30-car.
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*
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* The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
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* registers. These IDs often match those in the CAR's RST_DEVICES registers,
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* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
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* this case, those clocks are assigned IDs above 160 in order to highlight
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* this issue. Implementations that interpret these clock IDs as bit values
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* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
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* explicitly handle these special cases.
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*
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* The balance of the clocks controlled by the CAR are assigned IDs of 160 and
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* above.
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*/
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#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
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#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
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#define TEGRA30_CLK_CPU 0
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/* 1 */
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/* 2 */
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/* 3 */
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#define TEGRA30_CLK_RTC 4
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#define TEGRA30_CLK_TIMER 5
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#define TEGRA30_CLK_UARTA 6
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/* 7 (register bit affects uartb and vfir) */
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#define TEGRA30_CLK_GPIO 8
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#define TEGRA30_CLK_SDMMC2 9
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/* 10 (register bit affects spdif_in and spdif_out) */
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#define TEGRA30_CLK_I2S1 11
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#define TEGRA30_CLK_I2C1 12
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#define TEGRA30_CLK_NDFLASH 13
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#define TEGRA30_CLK_SDMMC1 14
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#define TEGRA30_CLK_SDMMC4 15
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/* 16 */
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#define TEGRA30_CLK_PWM 17
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#define TEGRA30_CLK_I2S2 18
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#define TEGRA30_CLK_EPP 19
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/* 20 (register bit affects vi and vi_sensor) */
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#define TEGRA30_CLK_GR2D 21
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#define TEGRA30_CLK_USBD 22
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#define TEGRA30_CLK_ISP 23
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#define TEGRA30_CLK_GR3D 24
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/* 25 */
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#define TEGRA30_CLK_DISP2 26
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#define TEGRA30_CLK_DISP1 27
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#define TEGRA30_CLK_HOST1X 28
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#define TEGRA30_CLK_VCP 29
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#define TEGRA30_CLK_I2S0 30
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#define TEGRA30_CLK_COP_CACHE 31
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#define TEGRA30_CLK_MC 32
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#define TEGRA30_CLK_AHBDMA 33
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#define TEGRA30_CLK_APBDMA 34
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/* 35 */
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#define TEGRA30_CLK_KBC 36
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#define TEGRA30_CLK_STATMON 37
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#define TEGRA30_CLK_PMC 38
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/* 39 (register bit affects fuse and fuse_burn) */
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#define TEGRA30_CLK_KFUSE 40
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#define TEGRA30_CLK_SBC1 41
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#define TEGRA30_CLK_NOR 42
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/* 43 */
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#define TEGRA30_CLK_SBC2 44
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/* 45 */
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#define TEGRA30_CLK_SBC3 46
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#define TEGRA30_CLK_I2C5 47
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#define TEGRA30_CLK_DSIA 48
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/* 49 (register bit affects cve and tvo) */
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#define TEGRA30_CLK_MIPI 50
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#define TEGRA30_CLK_HDMI 51
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#define TEGRA30_CLK_CSI 52
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#define TEGRA30_CLK_TVDAC 53
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#define TEGRA30_CLK_I2C2 54
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#define TEGRA30_CLK_UARTC 55
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/* 56 */
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#define TEGRA30_CLK_EMC 57
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#define TEGRA30_CLK_USB2 58
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#define TEGRA30_CLK_USB3 59
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#define TEGRA30_CLK_MPE 60
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#define TEGRA30_CLK_VDE 61
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#define TEGRA30_CLK_BSEA 62
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#define TEGRA30_CLK_BSEV 63
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#define TEGRA30_CLK_SPEEDO 64
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#define TEGRA30_CLK_UARTD 65
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#define TEGRA30_CLK_UARTE 66
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#define TEGRA30_CLK_I2C3 67
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#define TEGRA30_CLK_SBC4 68
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#define TEGRA30_CLK_SDMMC3 69
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#define TEGRA30_CLK_PCIE 70
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#define TEGRA30_CLK_OWR 71
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#define TEGRA30_CLK_AFI 72
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#define TEGRA30_CLK_CSITE 73
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/* 74 */
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#define TEGRA30_CLK_AVPUCQ 75
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#define TEGRA30_CLK_LA 76
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/* 77 */
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/* 78 */
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#define TEGRA30_CLK_DTV 79
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#define TEGRA30_CLK_NDSPEED 80
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#define TEGRA30_CLK_I2CSLOW 81
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#define TEGRA30_CLK_DSIB 82
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/* 83 */
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#define TEGRA30_CLK_IRAMA 84
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#define TEGRA30_CLK_IRAMB 85
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#define TEGRA30_CLK_IRAMC 86
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#define TEGRA30_CLK_IRAMD 87
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#define TEGRA30_CLK_CRAM2 88
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/* 89 */
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#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
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/* 91 */
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#define TEGRA30_CLK_CSUS 92
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#define TEGRA30_CLK_CDEV2 93
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#define TEGRA30_CLK_CDEV1 94
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/* 95 */
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#define TEGRA30_CLK_CPU_G 96
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#define TEGRA30_CLK_CPU_LP 97
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#define TEGRA30_CLK_GR3D2 98
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#define TEGRA30_CLK_MSELECT 99
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#define TEGRA30_CLK_TSENSOR 100
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#define TEGRA30_CLK_I2S3 101
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#define TEGRA30_CLK_I2S4 102
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#define TEGRA30_CLK_I2C4 103
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#define TEGRA30_CLK_SBC5 104
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#define TEGRA30_CLK_SBC6 105
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#define TEGRA30_CLK_D_AUDIO 106
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#define TEGRA30_CLK_APBIF 107
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#define TEGRA30_CLK_DAM0 108
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#define TEGRA30_CLK_DAM1 109
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#define TEGRA30_CLK_DAM2 110
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#define TEGRA30_CLK_HDA2CODEC_2X 111
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#define TEGRA30_CLK_ATOMICS 112
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#define TEGRA30_CLK_AUDIO0_2X 113
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#define TEGRA30_CLK_AUDIO1_2X 114
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#define TEGRA30_CLK_AUDIO2_2X 115
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#define TEGRA30_CLK_AUDIO3_2X 116
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#define TEGRA30_CLK_AUDIO4_2X 117
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#define TEGRA30_CLK_SPDIF_2X 118
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#define TEGRA30_CLK_ACTMON 119
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#define TEGRA30_CLK_EXTERN1 120
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#define TEGRA30_CLK_EXTERN2 121
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#define TEGRA30_CLK_EXTERN3 122
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#define TEGRA30_CLK_SATA_OOB 123
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#define TEGRA30_CLK_SATA 124
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#define TEGRA30_CLK_HDA 125
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/* 126 */
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#define TEGRA30_CLK_SE 127
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#define TEGRA30_CLK_HDA2HDMI 128
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#define TEGRA30_CLK_SATA_COLD 129
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/* 130 */
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/* 131 */
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/* 132 */
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/* 133 */
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/* 134 */
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/* 135 */
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/* 136 */
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/* 137 */
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/* 138 */
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/* 139 */
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/* 140 */
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/* 141 */
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/* 142 */
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/* 143 */
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/* 144 */
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/* 145 */
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/* 146 */
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/* 147 */
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/* 148 */
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/* 149 */
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/* 150 */
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/* 151 */
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/* 152 */
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/* 153 */
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/* 154 */
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/* 155 */
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/* 156 */
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/* 157 */
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/* 158 */
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/* 159 */
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#define TEGRA30_CLK_UARTB 160
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#define TEGRA30_CLK_VFIR 161
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#define TEGRA30_CLK_SPDIF_IN 162
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#define TEGRA30_CLK_SPDIF_OUT 163
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#define TEGRA30_CLK_VI 164
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#define TEGRA30_CLK_VI_SENSOR 165
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#define TEGRA30_CLK_FUSE 166
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#define TEGRA30_CLK_FUSE_BURN 167
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#define TEGRA30_CLK_CVE 168
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#define TEGRA30_CLK_TVO 169
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#define TEGRA30_CLK_CLK_32K 170
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#define TEGRA30_CLK_CLK_M 171
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#define TEGRA30_CLK_CLK_M_DIV2 172
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#define TEGRA30_CLK_CLK_M_DIV4 173
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#define TEGRA30_CLK_PLL_REF 174
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#define TEGRA30_CLK_PLL_C 175
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#define TEGRA30_CLK_PLL_C_OUT1 176
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#define TEGRA30_CLK_PLL_M 177
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#define TEGRA30_CLK_PLL_M_OUT1 178
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#define TEGRA30_CLK_PLL_P 179
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#define TEGRA30_CLK_PLL_P_OUT1 180
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#define TEGRA30_CLK_PLL_P_OUT2 181
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#define TEGRA30_CLK_PLL_P_OUT3 182
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#define TEGRA30_CLK_PLL_P_OUT4 183
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#define TEGRA30_CLK_PLL_A 184
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#define TEGRA30_CLK_PLL_A_OUT0 185
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#define TEGRA30_CLK_PLL_D 186
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#define TEGRA30_CLK_PLL_D_OUT0 187
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#define TEGRA30_CLK_PLL_D2 188
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#define TEGRA30_CLK_PLL_D2_OUT0 189
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#define TEGRA30_CLK_PLL_U 190
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#define TEGRA30_CLK_PLL_X 191
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#define TEGRA30_CLK_PLL_X_OUT0 192
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#define TEGRA30_CLK_PLL_E 193
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#define TEGRA30_CLK_SPDIF_IN_SYNC 194
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#define TEGRA30_CLK_I2S0_SYNC 195
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#define TEGRA30_CLK_I2S1_SYNC 196
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#define TEGRA30_CLK_I2S2_SYNC 197
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#define TEGRA30_CLK_I2S3_SYNC 198
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#define TEGRA30_CLK_I2S4_SYNC 199
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#define TEGRA30_CLK_VIMCLK_SYNC 200
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#define TEGRA30_CLK_AUDIO0 201
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#define TEGRA30_CLK_AUDIO1 202
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#define TEGRA30_CLK_AUDIO2 203
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#define TEGRA30_CLK_AUDIO3 204
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#define TEGRA30_CLK_AUDIO4 205
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#define TEGRA30_CLK_SPDIF 206
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#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
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#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
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#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
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#define TEGRA30_CLK_SCLK 210
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#define TEGRA30_CLK_BLINK 211
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#define TEGRA30_CLK_CCLK_G 212
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#define TEGRA30_CLK_CCLK_LP 213
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#define TEGRA30_CLK_TWD 214
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#define TEGRA30_CLK_CML0 215
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#define TEGRA30_CLK_CML1 216
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#define TEGRA30_CLK_HCLK 217
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#define TEGRA30_CLK_PCLK 218
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/* 219 */
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/* 220 */
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/* 221 */
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/* 222 */
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/* 223 */
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/* 288 */
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/* 289 */
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/* 290 */
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/* 291 */
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/* 292 */
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/* 293 */
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/* 294 */
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/* 295 */
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/* 296 */
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/* 297 */
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/* 298 */
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/* 299 */
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#define TEGRA30_CLK_CLK_OUT_1_MUX 300
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#define TEGRA30_CLK_CLK_OUT_2_MUX 301
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#define TEGRA30_CLK_CLK_OUT_3_MUX 302
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#define TEGRA30_CLK_AUDIO0_MUX 303
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#define TEGRA30_CLK_AUDIO1_MUX 304
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#define TEGRA30_CLK_AUDIO2_MUX 305
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#define TEGRA30_CLK_AUDIO3_MUX 306
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#define TEGRA30_CLK_AUDIO4_MUX 307
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#define TEGRA30_CLK_SPDIF_MUX 308
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#define TEGRA30_CLK_CLK_MAX 309
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#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
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