Andy Lutomirski 1e02ce4ccc x86: Store a per-cpu shadow copy of CR4 ... Context switches and TLB flushes can change individual bits of CR4. CR4 reads take several cycles, so store a shadow copy of CR4 in a per-cpu variable. To avoid wasting a cache line, I added the CR4 shadow to cpu_tlbstate, which is already touched in switch_mm. The heaviest users of the cr4 shadow will be switch_mm and __switch_to_xtra, and __switch_to_xtra is called shortly after switch_mm during context switch, so the cacheline is likely to be hot. Signed-off-by: Andy Lutomirski <luto@amacapital.net> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Kees Cook <keescook@chromium.org> Cc: Andrea Arcangeli <aarcange@redhat.com> Cc: Vince Weaver <vince@deater.net> Cc: "hillf.zj" <hillf.zj@alibaba-inc.com> Cc: Valdis Kletnieks <Valdis.Kletnieks@vt.edu> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: http://lkml.kernel.org/r/3a54dd3353fffbf84804398e00dfdc5b7c1afd7d.1414190806.git.luto@amacapital.net Signed-off-by: Ingo Molnar <mingo@kernel.org>		2015-02-04 12:10:42 +01:00
..
amd.c	x86, mtrr: Constify struct mtrr_ops	2010-02-01 11:20:43 -08:00
centaur.c	x86, mtrr: Constify struct mtrr_ops	2010-02-01 11:20:43 -08:00
cleanup.c	x86, mtrr: Fix original mtrr range get for mtrr_cleanup	2013-06-18 11:32:02 -05:00
cyrix.c	x86: Store a per-cpu shadow copy of CR4	2015-02-04 12:10:42 +01:00
generic.c	x86: Store a per-cpu shadow copy of CR4	2015-02-04 12:10:42 +01:00
if.c	x86, mtrr: Use explicit sizing and padding for the 64-bit ioctls	2012-03-01 12:48:52 -08:00
main.c	x86: Add more disabled features	2014-09-11 14:30:17 -07:00
Makefile	x86, mtrr: Remove unused mtrr/state.c	2010-02-04 10:01:38 +01:00
mtrr.h	x86, mtrr: Constify struct mtrr_ops	2010-02-01 11:20:43 -08:00