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e02f866456
There are a number of statements of the form A, B or A, B, C where the numbers A,B,C are consecutive. Tidy these up to be A-B or A-C as appropriate and to comply better with copyright standards [1] [1] http://www.copyrightservice.co.uk/copyright/p03_copyright_notices section 4iii 'Year of publication' Signed-off-by: Ben Dooks <ben@simtec.co.uk> Signed-off-by: Simtec Linux Team <linux@simtec.co.uk> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
89 lines
3.1 KiB
C
89 lines
3.1 KiB
C
/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
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*
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* Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C24A0 clock register definitions
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*/
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#ifndef __ASM_ARCH_24A0_REGS_CLOCK_H
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#define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__
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#define S3C24A0_MPLLCON S3C2410_CLKREG(0x10)
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#define S3C24A0_UPLLCON S3C2410_CLKREG(0x14)
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#define S3C24A0_CLKCON S3C2410_CLKREG(0x20)
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#define S3C24A0_CLKSRC S3C2410_CLKREG(0x24)
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#define S3C24A0_CLKDIVN S3C2410_CLKREG(0x28)
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/* CLKCON register bits */
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#define S3C24A0_CLKCON_VLX (1<<29)
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#define S3C24A0_CLKCON_VPOST (1<<28)
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#define S3C24A0_CLKCON_WDT (1<<27) /* reserved */
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#define S3C24A0_CLKCON_MPEGDCTQ (1<<26)
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#define S3C24A0_CLKCON_VPOSTIF (1<<25)
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#define S3C24A0_CLKCON_MPEG4IF (1<<24)
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#define S3C24A0_CLKCON_CAM_UPLL (1<<23)
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#define S3C24A0_CLKCON_LCDC (1<<22)
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#define S3C24A0_CLKCON_CAM_HCLK (1<<21)
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#define S3C24A0_CLKCON_MPEG4 (1<<20)
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#define S3C24A0_CLKCON_KEYPAD (1<<19)
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#define S3C24A0_CLKCON_ADC (1<<18)
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#define S3C24A0_CLKCON_SDI (1<<17)
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#define S3C24A0_CLKCON_MS (1<<16) /* memory stick */
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#define S3C24A0_CLKCON_USBD (1<<15)
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#define S3C24A0_CLKCON_GPIO (1<<14)
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#define S3C24A0_CLKCON_IIS (1<<13)
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#define S3C24A0_CLKCON_IIC (1<<12)
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#define S3C24A0_CLKCON_SPI (1<<11)
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#define S3C24A0_CLKCON_UART1 (1<<10)
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#define S3C24A0_CLKCON_UART0 (1<<9)
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#define S3C24A0_CLKCON_PWMT (1<<8)
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#define S3C24A0_CLKCON_USBH (1<<7)
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#define S3C24A0_CLKCON_AC97 (1<<6)
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#define S3C24A0_CLKCON_IrDA (1<<4)
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#define S3C24A0_CLKCON_IDLE (1<<2)
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#define S3C24A0_CLKCON_MON (1<<1)
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#define S3C24A0_CLKCON_STOP (1<<0)
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/* CLKSRC register bits */
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#define S3C24A0_CLKSRC_OSC (1<<8) /* CLKSRC */
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#define S3C24A0_CLKSRC_UPLL (1<<7)
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#define S3C24A0_CLKSRC_MPLL (1<<5)
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#define S3C24A0_CLKSRC_EXT (1<<4)
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/* Use a single interface with the common code, for s3c24xx */
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#define S3C2410_MPLLCON S3C24A0_MPLLCON
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#define S3C2410_UPLLCON S3C24A0_UPLLCON
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#define S3C2410_CLKCON S3C24A0_CLKCON
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#define S3C2410_CLKSLOW S3C24A0_CLKSRC
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#define S3C2410_CLKDIVN S3C24A0_CLKDIVN
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#define S3C2410_CLKCON_IDLE S3C24A0_CLKCON_IDLE
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#define S3C2410_CLKCON_POWER S3C24A0_CLKCON_STOP
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#define S3C2410_CLKCON_LCDC S3C24A0_CLKCON_LCDC
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#define S3C2410_CLKCON_USBH S3C24A0_CLKCON_USBH
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#define S3C2410_CLKCON_USBD S3C24A0_CLKCON_USBD
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#define S3C2410_CLKCON_PWMT S3C24A0_CLKCON_PWMT
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#define S3C2410_CLKCON_SDI S3C24A0_CLKCON_SDI
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#define S3C2410_CLKCON_UART0 S3C24A0_CLKCON_UART0
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#define S3C2410_CLKCON_UART1 S3C24A0_CLKCON_UART1
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#define S3C2410_CLKCON_GPIO S3C24A0_CLKCON_GPIO
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#define S3C2410_CLKCON_ADC S3C24A0_CLKCON_ADC
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#define S3C2410_CLKCON_IIC S3C24A0_CLKCON_IIC
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#define S3C2410_CLKCON_IIS S3C24A0_CLKCON_IIS
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#define S3C2410_CLKCON_SPI S3C24A0_CLKCON_SPI
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#define S3C2410_CLKSLOW_UCLK_OFF S3C24A0_CLKSRC_UPLL
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#define S3C2410_CLKSLOW_MPLL_OFF S3C24A0_CLKSRC_MPLL
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#define S3C2410_CLKSLOW_SLOW (0xFF)
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#define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1)
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#endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */
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