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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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79795e20a1
Add DT bindings for the Meson SoC Reset Controller documentation and the associated include file. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
211 lines
6.4 KiB
C
211 lines
6.4 KiB
C
/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING.
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*
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* BSD LICENSE
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*
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* Copyright (c) 2016 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
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/* RESET0 */
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#define RESET_HIU 0
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/* 1 */
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#define RESET_DOS_RESET 2
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#define RESET_DDR_TOP 3
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#define RESET_DCU_RESET 4
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#define RESET_VIU 5
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#define RESET_AIU 6
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#define RESET_VID_PLL_DIV 7
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/* 8 */
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#define RESET_PMUX 9
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#define RESET_VENC 10
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#define RESET_ASSIST 11
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#define RESET_AFIFO2 12
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#define RESET_VCBUS 13
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/* 14 */
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/* 15 */
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#define RESET_GIC 16
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#define RESET_CAPB3_DECODE 17
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#define RESET_NAND_CAPB3 18
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#define RESET_HDMITX_CAPB3 19
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#define RESET_MALI_CAPB3 20
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#define RESET_DOS_CAPB3 21
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#define RESET_SYS_CPU_CAPB3 22
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#define RESET_CBUS_CAPB3 23
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#define RESET_AHB_CNTL 24
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#define RESET_AHB_DATA 25
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#define RESET_VCBUS_CLK81 26
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#define RESET_MMC 27
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#define RESET_MIPI_0 28
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#define RESET_MIPI_1 29
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#define RESET_MIPI_2 30
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#define RESET_MIPI_3 31
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/* RESET1 */
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#define RESET_CPPM 32
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#define RESET_DEMUX 33
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#define RESET_USB_OTG 34
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#define RESET_DDR 35
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#define RESET_AO_RESET 36
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#define RESET_BT656 37
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#define RESET_AHB_SRAM 38
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/* 39 */
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#define RESET_PARSER 40
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#define RESET_BLKMV 41
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#define RESET_ISA 42
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#define RESET_ETHERNET 43
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#define RESET_SD_EMMC_A 44
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#define RESET_SD_EMMC_B 45
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#define RESET_SD_EMMC_C 46
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#define RESET_ROM_BOOT 47
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#define RESET_SYS_CPU_0 48
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#define RESET_SYS_CPU_1 49
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#define RESET_SYS_CPU_2 50
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#define RESET_SYS_CPU_3 51
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#define RESET_SYS_CPU_CORE_0 52
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#define RESET_SYS_CPU_CORE_1 53
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#define RESET_SYS_CPU_CORE_2 54
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#define RESET_SYS_CPU_CORE_3 55
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#define RESET_SYS_PLL_DIV 56
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#define RESET_SYS_CPU_AXI 57
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#define RESET_SYS_CPU_L2 58
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#define RESET_SYS_CPU_P 59
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#define RESET_SYS_CPU_MBIST 60
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/* 61 */
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/* 62 */
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/* 63 */
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/* RESET2 */
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#define RESET_VD_RMEM 64
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#define RESET_AUDIN 65
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#define RESET_HDMI_TX 66
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/* 67 */
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/* 68 */
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/* 69 */
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#define RESET_GE2D 70
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#define RESET_PARSER_REG 71
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#define RESET_PARSER_FETCH 72
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#define RESET_PARSER_CTL 73
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#define RESET_PARSER_TOP 74
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/* 75 */
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/* 76 */
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#define RESET_AO_CPU_RESET 77
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#define RESET_MALI 78
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#define RESET_HDMI_SYSTEM_RESET 79
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/* 80-95 */
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/* RESET3 */
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#define RESET_RING_OSCILLATOR 96
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#define RESET_SYS_CPU 97
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#define RESET_EFUSE 98
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#define RESET_SYS_CPU_BVCI 99
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#define RESET_AIFIFO 100
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#define RESET_TVFE 101
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#define RESET_AHB_BRIDGE_CNTL 102
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/* 103 */
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#define RESET_AUDIO_DAC 104
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#define RESET_DEMUX_TOP 105
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#define RESET_DEMUX_DES 106
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#define RESET_DEMUX_S2P_0 107
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#define RESET_DEMUX_S2P_1 108
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#define RESET_DEMUX_RESET_0 109
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#define RESET_DEMUX_RESET_1 110
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#define RESET_DEMUX_RESET_2 111
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/* 112-127 */
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/* RESET4 */
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/* 128 */
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/* 129 */
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/* 130 */
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/* 131 */
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#define RESET_DVIN_RESET 132
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#define RESET_RDMA 133
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#define RESET_VENCI 134
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#define RESET_VENCP 135
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/* 136 */
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#define RESET_VDAC 137
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#define RESET_RTC 138
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/* 139 */
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#define RESET_VDI6 140
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#define RESET_VENCL 141
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#define RESET_I2C_MASTER_2 142
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#define RESET_I2C_MASTER_1 143
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/* 144-159 */
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/* RESET5 */
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/* 160-191 */
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/* RESET6 */
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#define RESET_PERIPHS_GENERAL 192
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#define RESET_PERIPHS_SPICC 193
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#define RESET_PERIPHS_SMART_CARD 194
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#define RESET_PERIPHS_SAR_ADC 195
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#define RESET_PERIPHS_I2C_MASTER_0 196
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#define RESET_SANA 197
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/* 198 */
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#define RESET_PERIPHS_STREAM_INTERFACE 199
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#define RESET_PERIPHS_SDIO 200
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#define RESET_PERIPHS_UART_0 201
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#define RESET_PERIPHS_UART_1_2 202
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#define RESET_PERIPHS_ASYNC_0 203
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#define RESET_PERIPHS_ASYNC_1 204
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#define RESET_PERIPHS_SPI_0 205
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#define RESET_PERIPHS_SDHC 206
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#define RESET_UART_SLIP 207
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/* 208-223 */
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/* RESET7 */
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#define RESET_USB_DDR_0 224
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#define RESET_USB_DDR_1 225
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#define RESET_USB_DDR_2 226
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#define RESET_USB_DDR_3 227
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/* 228 */
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#define RESET_DEVICE_MMC_ARB 229
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/* 230 */
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#define RESET_VID_LOCK 231
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#define RESET_A9_DMC_PIPEL 232
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/* 233-255 */
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#endif
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