linux_dsm_epyc7002/arch/arm/mach-sti/board-dt.c
Patrice Chotard 0f77ce26eb Revert "ARM: sti: Implement dummy L2 cache's write_sec"
This reverts commit 7b8e0188fa.

Initially, STiH410-B2260 was supposed to be secured, that's why
l2c_write_sec was stubbed to avoid secure register access from
non secure world.

But by default, STiH410-B2260 is running in non secure mode,
so L2 cache register accesses are authorized, l2c_write_sec stub
is not needed.

With this patch, L2 cache is configured and performance are enhanced.

Link: https://lore.kernel.org/r/20200618172456.29475-1-patrice.chotard@st.com
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Cc: Alain Volmat <alain.volmat@st.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-06-28 14:46:54 +02:00

32 lines
763 B
C

// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
* Author(s): Srinivas Kandagatla <srinivas.kandagatla@st.com>
*/
#include <linux/irq.h>
#include <linux/of_platform.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include "smp.h"
static const char *const stih41x_dt_match[] __initconst = {
"st,stih415",
"st,stih416",
"st,stih407",
"st,stih410",
"st,stih418",
NULL
};
DT_MACHINE_START(STM, "STi SoC with Flattened Device Tree")
.dt_compat = stih41x_dt_match,
.l2c_aux_val = L2C_AUX_CTRL_SHARED_OVERRIDE |
L310_AUX_CTRL_DATA_PREFETCH |
L310_AUX_CTRL_INSTR_PREFETCH |
L2C_AUX_CTRL_WAY_SIZE(4),
.l2c_aux_mask = 0xc0000fff,
.smp = smp_ops(sti_smp_ops),
MACHINE_END