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c377925943
[ Upstream commit 47fa9a80270e20a0c4ddaffca1f144d22cc59620 ]
As part of the enable sequence we might change the HSM clock rate if the
pixel rate is different than the one we were already dealing with.
On the BCM2835 however, the CEC clock derives from the HSM clock so any
rate change will need to be reflected in the CEC clock divider to output
40kHz.
Fixes:
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.. | ||
drm | ||
host1x | ||
ipu-v3 | ||
trace | ||
vga | ||
Makefile |