mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 11:29:53 +07:00
773b4b5435
Move all of haswell_crtc_disable() into the encoder .post_disable() hooks. Now we're left with just calling the .disable() and .post_disable() hooks back to back. I chose to move the code into the .post_disable() hook instead of the .disable() hook as most of the sequence is currently implemented in the .post_disable() hook. We should collapse it all down to just one hook and then the encoders can drive the modeset sequence fully. But that may need some further refactoring as we currently call the ddi .post_disable() hook from mst code and we can't just replace that with a call to the ddi .disable() hook. Should also follow up with similar treatment for the enable sequence but let's start here where it's easier. Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191213195217.15168-5-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
649 lines
21 KiB
C
649 lines
21 KiB
C
/*
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* Copyright © 2006-2019 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef _INTEL_DISPLAY_H_
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#define _INTEL_DISPLAY_H_
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#include <drm/drm_util.h>
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#include <drm/i915_drm.h>
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enum link_m_n_set;
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struct dpll;
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struct drm_connector;
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struct drm_device;
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struct drm_display_mode;
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struct drm_encoder;
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struct drm_file;
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struct drm_format_info;
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struct drm_framebuffer;
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struct drm_i915_error_state_buf;
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struct drm_i915_gem_object;
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struct drm_i915_private;
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struct drm_modeset_acquire_ctx;
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struct drm_plane;
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struct drm_plane_state;
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struct i915_ggtt_view;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_digital_port;
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struct intel_dp;
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struct intel_encoder;
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struct intel_load_detect_pipe;
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struct intel_plane;
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struct intel_plane_state;
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struct intel_remapped_info;
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struct intel_rotation_info;
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struct intel_crtc_state;
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enum i915_gpio {
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GPIOA,
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GPIOB,
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GPIOC,
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GPIOD,
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GPIOE,
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GPIOF,
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GPIOG,
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GPIOH,
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__GPIOI_UNUSED,
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GPIOJ,
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GPIOK,
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GPIOL,
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GPIOM,
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GPION,
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GPIOO,
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};
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/*
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* Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
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* rest have consecutive values and match the enum values of transcoders
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* with a 1:1 transcoder -> pipe mapping.
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*/
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enum pipe {
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INVALID_PIPE = -1,
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PIPE_A = 0,
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PIPE_B,
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PIPE_C,
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PIPE_D,
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_PIPE_EDP,
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I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
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INVALID_TRANSCODER = -1,
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/*
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* The following transcoders have a 1:1 transcoder -> pipe mapping,
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* keep their values fixed: the code assumes that TRANSCODER_A=0, the
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* rest have consecutive values and match the enum values of the pipes
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* they map to.
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*/
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TRANSCODER_A = PIPE_A,
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TRANSCODER_B = PIPE_B,
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TRANSCODER_C = PIPE_C,
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TRANSCODER_D = PIPE_D,
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/*
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* The following transcoders can map to any pipe, their enum value
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* doesn't need to stay fixed.
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*/
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TRANSCODER_EDP,
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TRANSCODER_DSI_0,
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TRANSCODER_DSI_1,
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TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
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TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
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I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
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{
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switch (transcoder) {
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case TRANSCODER_A:
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return "A";
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case TRANSCODER_B:
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return "B";
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case TRANSCODER_C:
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return "C";
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case TRANSCODER_D:
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return "D";
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case TRANSCODER_EDP:
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return "EDP";
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case TRANSCODER_DSI_A:
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return "DSI A";
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case TRANSCODER_DSI_C:
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return "DSI C";
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default:
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return "<invalid>";
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}
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}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
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{
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return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
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}
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/*
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* Global legacy plane identifier. Valid only for primary/sprite
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* planes on pre-g4x, and only for primary planes on g4x-bdw.
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*/
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enum i9xx_plane_id {
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PLANE_A,
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PLANE_B,
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PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
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/*
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* Per-pipe plane identifier.
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* I915_MAX_PLANES in the enum below is the maximum (across all platforms)
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* number of planes per CRTC. Not all platforms really have this many planes,
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* which means some arrays of size I915_MAX_PLANES may have unused entries
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* between the topmost sprite plane and the cursor plane.
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*
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* This is expected to be passed to various register macros
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* (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
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*/
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enum plane_id {
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PLANE_PRIMARY,
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PLANE_SPRITE0,
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PLANE_SPRITE1,
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PLANE_SPRITE2,
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PLANE_SPRITE3,
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PLANE_SPRITE4,
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PLANE_SPRITE5,
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PLANE_CURSOR,
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I915_MAX_PLANES,
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};
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#define for_each_plane_id_on_crtc(__crtc, __p) \
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for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
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for_each_if((__crtc)->plane_ids_mask & BIT(__p))
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enum port {
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PORT_NONE = -1,
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PORT_A = 0,
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PORT_B,
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PORT_C,
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PORT_D,
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PORT_E,
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PORT_F,
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PORT_G,
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PORT_H,
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PORT_I,
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I915_MAX_PORTS
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};
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#define port_name(p) ((p) + 'A')
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/*
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* Ports identifier referenced from other drivers.
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* Expected to remain stable over time
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*/
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static inline const char *port_identifier(enum port port)
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{
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switch (port) {
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case PORT_A:
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return "Port A";
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case PORT_B:
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return "Port B";
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case PORT_C:
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return "Port C";
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case PORT_D:
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return "Port D";
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case PORT_E:
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return "Port E";
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case PORT_F:
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return "Port F";
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case PORT_G:
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return "Port G";
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case PORT_H:
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return "Port H";
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case PORT_I:
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return "Port I";
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default:
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return "<invalid>";
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}
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}
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enum tc_port {
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PORT_TC_NONE = -1,
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PORT_TC1 = 0,
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PORT_TC2,
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PORT_TC3,
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PORT_TC4,
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PORT_TC5,
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PORT_TC6,
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I915_MAX_TC_PORTS
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};
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enum tc_port_mode {
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TC_PORT_TBT_ALT,
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TC_PORT_DP_ALT,
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TC_PORT_LEGACY,
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};
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enum dpio_channel {
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DPIO_CH0,
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DPIO_CH1
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};
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enum dpio_phy {
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DPIO_PHY0,
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DPIO_PHY1,
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DPIO_PHY2,
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};
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#define I915_NUM_PHYS_VLV 2
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enum aux_ch {
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AUX_CH_A,
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AUX_CH_B,
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AUX_CH_C,
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AUX_CH_D,
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AUX_CH_E, /* ICL+ */
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AUX_CH_F,
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AUX_CH_G,
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};
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#define aux_ch_name(a) ((a) + 'A')
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/* Used by dp and fdi links */
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struct intel_link_m_n {
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u32 tu;
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u32 gmch_m;
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u32 gmch_n;
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u32 link_m;
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u32 link_n;
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};
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enum phy {
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PHY_NONE = -1,
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PHY_A = 0,
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PHY_B,
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PHY_C,
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PHY_D,
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PHY_E,
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PHY_F,
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PHY_G,
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PHY_H,
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PHY_I,
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I915_MAX_PHYS
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};
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#define phy_name(a) ((a) + 'A')
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enum phy_fia {
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FIA1,
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FIA2,
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FIA3,
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};
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#define for_each_pipe(__dev_priv, __p) \
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for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
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for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) \
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for_each_if((__mask) & BIT(__p))
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#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
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for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
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for_each_if ((__mask) & (1 << (__t)))
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#define for_each_universal_plane(__dev_priv, __pipe, __p) \
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for ((__p) = 0; \
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(__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
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(__p)++)
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#define for_each_sprite(__dev_priv, __p, __s) \
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for ((__s) = 0; \
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(__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
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(__s)++)
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#define for_each_port(__port) \
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for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
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#define for_each_port_masked(__port, __ports_mask) \
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for_each_port(__port) \
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for_each_if((__ports_mask) & BIT(__port))
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#define for_each_phy_masked(__phy, __phys_mask) \
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for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
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for_each_if((__phys_mask) & BIT(__phy))
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#define for_each_crtc(dev, crtc) \
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list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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#define for_each_intel_plane(dev, intel_plane) \
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list_for_each_entry(intel_plane, \
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&(dev)->mode_config.plane_list, \
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base.head)
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#define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
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list_for_each_entry(intel_plane, \
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&(dev)->mode_config.plane_list, \
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base.head) \
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for_each_if((plane_mask) & \
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drm_plane_mask(&intel_plane->base))
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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
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list_for_each_entry(intel_plane, \
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&(dev)->mode_config.plane_list, \
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base.head) \
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for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc) \
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list_for_each_entry(intel_crtc, \
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&(dev)->mode_config.crtc_list, \
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base.head)
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#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
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list_for_each_entry(intel_crtc, \
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&(dev)->mode_config.crtc_list, \
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base.head) \
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for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
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#define for_each_intel_encoder(dev, intel_encoder) \
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list_for_each_entry(intel_encoder, \
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&(dev)->mode_config.encoder_list, \
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base.head)
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#define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
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list_for_each_entry(intel_encoder, \
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&(dev)->mode_config.encoder_list, \
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base.head) \
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for_each_if((encoder_mask) & \
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drm_encoder_mask(&intel_encoder->base))
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#define for_each_intel_dp(dev, intel_encoder) \
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for_each_intel_encoder(dev, intel_encoder) \
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for_each_if(intel_encoder_is_dp(intel_encoder))
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#define for_each_intel_connector_iter(intel_connector, iter) \
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while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
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list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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for_each_if((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
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list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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for_each_if((intel_connector)->base.encoder == (__encoder))
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#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
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for ((__i) = 0; \
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(__i) < (__state)->base.dev->mode_config.num_total_plane && \
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((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
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(old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
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(__i)++) \
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for_each_if(plane)
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#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
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for ((__i) = 0; \
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(__i) < (__state)->base.dev->mode_config.num_total_plane && \
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((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
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(new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
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(__i)++) \
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for_each_if(plane)
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#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
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for ((__i) = 0; \
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(__i) < (__state)->base.dev->mode_config.num_crtc && \
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((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
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(new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
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(__i)++) \
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for_each_if(crtc)
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#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
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for ((__i) = 0; \
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(__i) < (__state)->base.dev->mode_config.num_total_plane && \
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((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
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(old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
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(new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
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(__i)++) \
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for_each_if(plane)
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#define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
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for ((__i) = 0; \
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(__i) < (__state)->base.dev->mode_config.num_crtc && \
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((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
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(old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
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(new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
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(__i)++) \
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for_each_if(crtc)
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#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
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for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
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(__i) >= 0 && \
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((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
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(old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
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(new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
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(__i)--) \
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for_each_if(crtc)
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#define intel_atomic_crtc_state_for_each_plane_state( \
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plane, plane_state, \
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crtc_state) \
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for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
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((crtc_state)->uapi.plane_mask)) \
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for_each_if ((plane_state = \
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to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
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#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
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for ((__i) = 0; \
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(__i) < (__state)->base.num_connector; \
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(__i)++) \
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for_each_if ((__state)->base.connectors[__i].ptr && \
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((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
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(new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
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void intel_link_compute_m_n(u16 bpp, int nlanes,
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int pixel_clock, int link_clock,
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struct intel_link_m_n *m_n,
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bool constant_n, bool fec_enable);
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bool is_ccs_modifier(u64 modifier);
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void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
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u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
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u32 pixel_format, u64 modifier);
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bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
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enum drm_mode_status
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intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
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const struct drm_display_mode *mode);
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enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
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bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
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void intel_plane_destroy(struct drm_plane *plane);
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void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state);
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void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
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void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
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enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
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int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
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int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
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const char *name, u32 reg, int ref_freq);
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int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
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const char *name, u32 reg);
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void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
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void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
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void intel_init_display_hooks(struct drm_i915_private *dev_priv);
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unsigned int intel_fb_xy_to_linear(int x, int y,
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const struct intel_plane_state *state,
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int plane);
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unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
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int color_plane, unsigned int height);
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void intel_add_fb_offsets(int *x, int *y,
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const struct intel_plane_state *state, int plane);
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unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
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unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
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bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
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int intel_display_suspend(struct drm_device *dev);
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void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
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void intel_encoder_destroy(struct drm_encoder *encoder);
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struct drm_display_mode *
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intel_encoder_current_mode(struct intel_encoder *encoder);
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bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
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bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
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enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
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enum port port);
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int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
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void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
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int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
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void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
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struct intel_digital_port *dport,
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unsigned int expected_mask);
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int intel_get_load_detect_pipe(struct drm_connector *connector,
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struct intel_load_detect_pipe *old,
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struct drm_modeset_acquire_ctx *ctx);
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void intel_release_load_detect_pipe(struct drm_connector *connector,
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struct intel_load_detect_pipe *old,
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struct drm_modeset_acquire_ctx *ctx);
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struct i915_vma *
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intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
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const struct i915_ggtt_view *view,
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bool uses_fence,
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unsigned long *out_flags);
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void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
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struct drm_framebuffer *
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intel_framebuffer_create(struct drm_i915_gem_object *obj,
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struct drm_mode_fb_cmd2 *mode_cmd);
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int intel_prepare_plane_fb(struct drm_plane *plane,
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struct drm_plane_state *new_state);
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void intel_cleanup_plane_fb(struct drm_plane *plane,
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struct drm_plane_state *old_state);
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void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
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enum pipe pipe);
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int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
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const struct dpll *dpll);
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void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
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int lpt_get_iclkip(struct drm_i915_private *dev_priv);
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bool intel_fuzzy_clock_check(int clock1, int clock2);
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void intel_prepare_reset(struct drm_i915_private *dev_priv);
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void intel_finish_reset(struct drm_i915_private *dev_priv);
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void intel_dp_get_m_n(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config);
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void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
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enum link_m_n_set m_n);
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int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
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bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
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struct dpll *best_clock);
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int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
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bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
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void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
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void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
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enum intel_display_power_domain intel_port_to_power_domain(enum port port);
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enum intel_display_power_domain
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intel_aux_power_domain(struct intel_digital_port *dig_port);
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void intel_mode_from_pipe_config(struct drm_display_mode *mode,
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struct intel_crtc_state *pipe_config);
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void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state);
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u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
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int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
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void skylake_scaler_disable(const struct intel_crtc_state *old_crtc_state);
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void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
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u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
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|
u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state);
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u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
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u32 skl_plane_stride(const struct intel_plane_state *plane_state,
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int plane);
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int skl_check_plane_surface(struct intel_plane_state *plane_state);
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int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
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|
int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
|
|
unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
|
|
u32 pixel_format, u64 modifier,
|
|
unsigned int rotation);
|
|
int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
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|
|
|
struct intel_display_error_state *
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intel_display_capture_error_state(struct drm_i915_private *dev_priv);
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|
void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
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struct intel_display_error_state *error);
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|
|
/* modesetting */
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|
void intel_modeset_init_hw(struct drm_i915_private *i915);
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|
int intel_modeset_init(struct drm_i915_private *i915);
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|
void intel_modeset_driver_remove(struct drm_i915_private *i915);
|
|
void intel_display_resume(struct drm_device *dev);
|
|
void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
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|
|
|
/* modesetting asserts */
|
|
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe);
|
|
void assert_pll(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe, bool state);
|
|
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
|
|
#define assert_pll_disabled(d, p) assert_pll(d, p, false)
|
|
void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
|
|
#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
|
|
#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
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void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe, bool state);
|
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#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
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#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
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void assert_pipe(struct drm_i915_private *dev_priv,
|
|
enum transcoder cpu_transcoder, bool state);
|
|
#define assert_pipe_enabled(d, t) assert_pipe(d, t, true)
|
|
#define assert_pipe_disabled(d, t) assert_pipe(d, t, false)
|
|
|
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
|
|
* WARN_ON()) for hw state sanity checks to check for unexpected conditions
|
|
* which may not necessarily be a user visible problem. This will either
|
|
* WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
|
|
* enable distros and users to tailor their preferred amount of i915 abrt
|
|
* spam.
|
|
*/
|
|
#define I915_STATE_WARN(condition, format...) ({ \
|
|
int __ret_warn_on = !!(condition); \
|
|
if (unlikely(__ret_warn_on)) \
|
|
if (!WARN(i915_modparams.verbose_state_checks, format)) \
|
|
DRM_ERROR(format); \
|
|
unlikely(__ret_warn_on); \
|
|
})
|
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|
|
#define I915_STATE_WARN_ON(x) \
|
|
I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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|
|
#endif
|