Sonika Jindal c3346ef688 drm/i915/skl: Program PLL for edp1.4 intermediate frequencies ... v2: Making the link_clock half in switch inline with the DPLL_CTRL1_* macros (Ville) Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2015-03-17 22:29:57 +01:00
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drm	drm/i915/skl: Program PLL for edp1.4 intermediate frequencies	2015-03-17 22:29:57 +01:00
host1x	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00
ipu-v3	gpu: ipu-v3: do not divide by zero if the pixel clock is too large	2015-02-23 17:18:59 +01:00
vga	Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2014-10-13 16:23:15 +02:00
Makefile	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00