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This accelerator is found inside hisilicon hip06 and hip07 SoCs. Each instance provides a number of queues which feed a different number of backend acceleration units. The queues are operating in an out of order mode in the interests of throughput. The silicon does not do tracking of dependencies between multiple 'messages' or update of the IVs as appropriate for training. Hence where relevant we need to do this in software. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
15 lines
401 B
Plaintext
15 lines
401 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config CRYPTO_DEV_HISI_SEC
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tristate "Support for Hisilicon SEC crypto block cipher accelerator"
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select CRYPTO_BLKCIPHER
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select CRYPTO_ALGAPI
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select SG_SPLIT
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depends on ARM64 || COMPILE_TEST
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depends on HAS_IOMEM
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help
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Support for Hisilicon SEC Engine in Hip06 and Hip07
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To compile this as a module, choose M here: the module
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will be called hisi_sec.
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