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397049a030
Setting bit5 (headerless msg for preemptible GPGPU context) of SAMPLER_MODE register to enable support for the headless msgs on gen11. None of existing use cases will be affected by this as this change makes both types of message - headerless and w/ header supported at the same time. It also complies with the new recommendation for the default bit value for the next gen. v2: rewrote commit message to include more information v3: setting the bit in icl_ctx_workarounds_init() Signed-off-by: Dongwon Kim <dongwon.kim@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190425055005.21790-1-chris@chris-wilson.co.uk Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> |
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| .. | ||
| intel_breadcrumbs.c | ||
| intel_context_types.h | ||
| intel_context.c | ||
| intel_context.h | ||
| intel_engine_cs.c | ||
| intel_engine_pm.c | ||
| intel_engine_pm.h | ||
| intel_engine_types.h | ||
| intel_engine.h | ||
| intel_gpu_commands.h | ||
| intel_gt_pm.c | ||
| intel_gt_pm.h | ||
| intel_hangcheck.c | ||
| intel_lrc_reg.h | ||
| intel_lrc.c | ||
| intel_lrc.h | ||
| intel_mocs.c | ||
| intel_mocs.h | ||
| intel_reset.c | ||
| intel_reset.h | ||
| intel_ringbuffer.c | ||
| intel_sseu.c | ||
| intel_sseu.h | ||
| intel_workarounds_types.h | ||
| intel_workarounds.c | ||
| intel_workarounds.h | ||
| Makefile | ||
| Makefile.header-test | ||
| mock_engine.c | ||
| mock_engine.h | ||
| selftest_engine_cs.c | ||
| selftest_hangcheck.c | ||
| selftest_lrc.c | ||
| selftest_reset.c | ||
| selftest_workarounds.c | ||