mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
105 lines
3.3 KiB
C
105 lines
3.3 KiB
C
/*
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* arch/v850/kernel/v850e_intc.c -- V850E interrupt controller (INTC)
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/v850e_intc.h>
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static void irq_nop (unsigned irq) { }
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static unsigned v850e_intc_irq_startup (unsigned irq)
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{
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v850e_intc_clear_pending_irq (irq);
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v850e_intc_enable_irq (irq);
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return 0;
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}
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static void v850e_intc_end_irq (unsigned irq)
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{
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unsigned long psw, temp;
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/* Clear the highest-level bit in the In-service priority register
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(ISPR), to allow this interrupt (or another of the same or
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lesser priority) to happen again.
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The `reti' instruction normally does this automatically when the
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PSW bits EP and NP are zero, but we can't always rely on reti
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being used consistently to return after an interrupt (another
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process can be scheduled, for instance, which can delay the
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associated reti for a long time, or this process may be being
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single-stepped, which uses the `dbret' instruction to return
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from the kernel).
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We also set the PSW EP bit, which prevents reti from also
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trying to modify the ISPR itself. */
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/* Get PSW and disable interrupts. */
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asm volatile ("stsr psw, %0; di" : "=r" (psw));
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/* We don't want to do anything for NMIs (they don't use the ISPR). */
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if (! (psw & 0xC0)) {
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/* Transition to `trap' state, so that an eventual real
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reti instruction won't modify the ISPR. */
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psw |= 0x40;
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/* Fake an interrupt return, which automatically clears the
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appropriate bit in the ISPR. */
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asm volatile ("mov hilo(1f), %0;"
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"ldsr %0, eipc; ldsr %1, eipsw;"
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"reti;"
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"1:"
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: "=&r" (temp) : "r" (psw));
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}
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}
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/* Initialize HW_IRQ_TYPES for INTC-controlled irqs described in array
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INITS (which is terminated by an entry with the name field == 0). */
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void __init v850e_intc_init_irq_types (struct v850e_intc_irq_init *inits,
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struct hw_interrupt_type *hw_irq_types)
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{
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struct v850e_intc_irq_init *init;
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for (init = inits; init->name; init++) {
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unsigned i;
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struct hw_interrupt_type *hwit = hw_irq_types++;
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hwit->typename = init->name;
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hwit->startup = v850e_intc_irq_startup;
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hwit->shutdown = v850e_intc_disable_irq;
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hwit->enable = v850e_intc_enable_irq;
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hwit->disable = v850e_intc_disable_irq;
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hwit->ack = irq_nop;
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hwit->end = v850e_intc_end_irq;
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/* Initialize kernel IRQ infrastructure for this interrupt. */
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init_irq_handlers(init->base, init->num, init->interval, hwit);
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/* Set the interrupt priorities. */
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for (i = 0; i < init->num; i++) {
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unsigned irq = init->base + i * init->interval;
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/* If the interrupt is currently enabled (all
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interrupts are initially disabled), then
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assume whoever enabled it has set things up
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properly, and avoid messing with it. */
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if (! v850e_intc_irq_enabled (irq))
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/* This write also (1) disables the
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interrupt, and (2) clears any pending
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interrupts. */
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V850E_INTC_IC (irq)
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= (V850E_INTC_IC_PR (init->priority)
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| V850E_INTC_IC_MK);
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}
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}
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}
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