mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 13:36:46 +07:00
5d8544e2d0
This patch contains code that is more specific to the RISC-V ISA than it is to Linux. It contains string and math operations, C wrappers for various assembly instructions, stack walking code, and uaccess. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
116 lines
2.5 KiB
ArmAsm
116 lines
2.5 KiB
ArmAsm
/*
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* Copyright (C) 2013 Regents of the University of California
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/linkage.h>
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#include <asm/asm.h>
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/* void *memcpy(void *, const void *, size_t) */
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ENTRY(memcpy)
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move t6, a0 /* Preserve return value */
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/* Defer to byte-oriented copy for small sizes */
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sltiu a3, a2, 128
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bnez a3, 4f
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/* Use word-oriented copy only if low-order bits match */
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andi a3, t6, SZREG-1
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andi a4, a1, SZREG-1
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bne a3, a4, 4f
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beqz a3, 2f /* Skip if already aligned */
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/*
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* Round to nearest double word-aligned address
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* greater than or equal to start address
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*/
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andi a3, a1, ~(SZREG-1)
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addi a3, a3, SZREG
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/* Handle initial misalignment */
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sub a4, a3, a1
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1:
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lb a5, 0(a1)
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addi a1, a1, 1
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sb a5, 0(t6)
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addi t6, t6, 1
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bltu a1, a3, 1b
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sub a2, a2, a4 /* Update count */
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2:
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andi a4, a2, ~((16*SZREG)-1)
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beqz a4, 4f
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add a3, a1, a4
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3:
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REG_L a4, 0(a1)
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REG_L a5, SZREG(a1)
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REG_L a6, 2*SZREG(a1)
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REG_L a7, 3*SZREG(a1)
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REG_L t0, 4*SZREG(a1)
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REG_L t1, 5*SZREG(a1)
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REG_L t2, 6*SZREG(a1)
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REG_L t3, 7*SZREG(a1)
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REG_L t4, 8*SZREG(a1)
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REG_L t5, 9*SZREG(a1)
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REG_S a4, 0(t6)
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REG_S a5, SZREG(t6)
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REG_S a6, 2*SZREG(t6)
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REG_S a7, 3*SZREG(t6)
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REG_S t0, 4*SZREG(t6)
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REG_S t1, 5*SZREG(t6)
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REG_S t2, 6*SZREG(t6)
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REG_S t3, 7*SZREG(t6)
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REG_S t4, 8*SZREG(t6)
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REG_S t5, 9*SZREG(t6)
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REG_L a4, 10*SZREG(a1)
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REG_L a5, 11*SZREG(a1)
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REG_L a6, 12*SZREG(a1)
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REG_L a7, 13*SZREG(a1)
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REG_L t0, 14*SZREG(a1)
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REG_L t1, 15*SZREG(a1)
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addi a1, a1, 16*SZREG
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REG_S a4, 10*SZREG(t6)
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REG_S a5, 11*SZREG(t6)
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REG_S a6, 12*SZREG(t6)
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REG_S a7, 13*SZREG(t6)
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REG_S t0, 14*SZREG(t6)
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REG_S t1, 15*SZREG(t6)
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addi t6, t6, 16*SZREG
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bltu a1, a3, 3b
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andi a2, a2, (16*SZREG)-1 /* Update count */
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4:
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/* Handle trailing misalignment */
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beqz a2, 6f
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add a3, a1, a2
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/* Use word-oriented copy if co-aligned to word boundary */
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or a5, a1, t6
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or a5, a5, a3
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andi a5, a5, 3
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bnez a5, 5f
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7:
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lw a4, 0(a1)
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addi a1, a1, 4
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sw a4, 0(t6)
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addi t6, t6, 4
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bltu a1, a3, 7b
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ret
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5:
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lb a4, 0(a1)
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addi a1, a1, 1
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sb a4, 0(t6)
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addi t6, t6, 1
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bltu a1, a3, 5b
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6:
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ret
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END(memcpy)
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