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1496878a74
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Link: https://lore.kernel.org/r/20200713112657.33694-1-grandmaster@al2klimov.de
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
204 lines
8.0 KiB
ReStructuredText
204 lines
8.0 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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============
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I3C protocol
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============
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Disclaimer
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==========
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This chapter will focus on aspects that matter to software developers. For
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everything hardware related (like how things are transmitted on the bus, how
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collisions are prevented, ...) please have a look at the I3C specification.
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This document is just a brief introduction to the I3C protocol and the concepts
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it brings to the table. If you need more information, please refer to the MIPI
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I3C specification (can be downloaded here
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https://resources.mipi.org/mipi-i3c-v1-download).
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Introduction
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============
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The I3C (pronounced 'eye-three-see') is a MIPI standardized protocol designed
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to overcome I2C limitations (limited speed, external signals needed for
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interrupts, no automatic detection of the devices connected to the bus, ...)
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while remaining power-efficient.
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I3C Bus
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=======
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An I3C bus is made of several I3C devices and possibly some I2C devices as
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well, but let's focus on I3C devices for now.
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An I3C device on the I3C bus can have one of the following roles:
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* Master: the device is driving the bus. It's the one in charge of initiating
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transactions or deciding who is allowed to talk on the bus (slave generated
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events are possible in I3C, see below).
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* Slave: the device acts as a slave, and is not able to send frames to another
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slave on the bus. The device can still send events to the master on
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its own initiative if the master allowed it.
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I3C is a multi-master protocol, so there might be several masters on a bus,
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though only one device can act as a master at a given time. In order to gain
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bus ownership, a master has to follow a specific procedure.
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Each device on the I3C bus has to be assigned a dynamic address to be able to
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communicate. Until this is done, the device should only respond to a limited
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set of commands. If it has a static address (also called legacy I2C address),
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the device can reply to I2C transfers.
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In addition to these per-device addresses, the protocol defines a broadcast
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address in order to address all devices on the bus.
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Once a dynamic address has been assigned to a device, this address will be used
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for any direct communication with the device. Note that even after being
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assigned a dynamic address, the device should still process broadcast messages.
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I3C Device discovery
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====================
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The I3C protocol defines a mechanism to automatically discover devices present
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on the bus, their capabilities and the functionalities they provide. In this
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regard I3C is closer to a discoverable bus like USB than it is to I2C or SPI.
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The discovery mechanism is called DAA (Dynamic Address Assignment), because it
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not only discovers devices but also assigns them a dynamic address.
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During DAA, each I3C device reports 3 important things:
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* BCR: Bus Characteristic Register. This 8-bit register describes the device bus
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related capabilities
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* DCR: Device Characteristic Register. This 8-bit register describes the
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functionalities provided by the device
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* Provisional ID: A 48-bit unique identifier. On a given bus there should be no
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Provisional ID collision, otherwise the discovery mechanism may fail.
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I3C slave events
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================
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The I3C protocol allows slaves to generate events on their own, and thus allows
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them to take temporary control of the bus.
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This mechanism is called IBI for In Band Interrupts, and as stated in the name,
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it allows devices to generate interrupts without requiring an external signal.
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During DAA, each device on the bus has been assigned an address, and this
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address will serve as a priority identifier to determine who wins if 2 different
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devices are generating an interrupt at the same moment on the bus (the lower the
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dynamic address the higher the priority).
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Masters are allowed to inhibit interrupts if they want to. This inhibition
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request can be broadcast (applies to all devices) or sent to a specific
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device.
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I3C Hot-Join
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============
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The Hot-Join mechanism is similar to USB hotplug. This mechanism allows
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slaves to join the bus after it has been initialized by the master.
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This covers the following use cases:
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* the device is not powered when the bus is probed
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* the device is hotplugged on the bus through an extension board
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This mechanism is relying on slave events to inform the master that a new
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device joined the bus and is waiting for a dynamic address.
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The master is then free to address the request as it wishes: ignore it or
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assign a dynamic address to the slave.
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I3C transfer types
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==================
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If you omit SMBus (which is just a standardization on how to access registers
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exposed by I2C devices), I2C has only one transfer type.
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I3C defines 3 different classes of transfer in addition to I2C transfers which
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are here for backward compatibility with I2C devices.
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I3C CCC commands
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----------------
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CCC (Common Command Code) commands are meant to be used for anything that is
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related to bus management and all features that are common to a set of devices.
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CCC commands contain an 8-bit CCC ID describing the command that is executed.
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The MSB of this ID specifies whether this is a broadcast command (bit7 = 0) or a
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unicast one (bit7 = 1).
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The command ID can be followed by a payload. Depending on the command, this
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payload is either sent by the master sending the command (write CCC command),
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or sent by the slave receiving the command (read CCC command). Of course, read
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accesses only apply to unicast commands.
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Note that, when sending a CCC command to a specific device, the device address
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is passed in the first byte of the payload.
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The payload length is not explicitly passed on the bus, and should be extracted
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from the CCC ID.
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Note that vendors can use a dedicated range of CCC IDs for their own commands
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(0x61-0x7f and 0xe0-0xef).
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I3C Private SDR transfers
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-------------------------
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Private SDR (Single Data Rate) transfers should be used for anything that is
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device specific and does not require high transfer speed.
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It is the equivalent of I2C transfers but in the I3C world. Each transfer is
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passed the device address (dynamic address assigned during DAA), a payload
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and a direction.
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The only difference with I2C is that the transfer is much faster (typical clock
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frequency is 12.5MHz).
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I3C HDR commands
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----------------
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HDR commands should be used for anything that is device specific and requires
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high transfer speed.
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The first thing attached to an HDR command is the HDR mode. There are currently
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3 different modes defined by the I3C specification (refer to the specification
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for more details):
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* HDR-DDR: Double Data Rate mode
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* HDR-TSP: Ternary Symbol Pure. Only usable on busses with no I2C devices
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* HDR-TSL: Ternary Symbol Legacy. Usable on busses with I2C devices
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When sending an HDR command, the whole bus has to enter HDR mode, which is done
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using a broadcast CCC command.
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Once the bus has entered a specific HDR mode, the master sends the HDR command.
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An HDR command is made of:
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* one 16-bits command word in big endian
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* N 16-bits data words in big endian
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Those words may be wrapped with specific preambles/post-ambles which depend on
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the chosen HDR mode and are detailed here (see the specification for more
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details).
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The 16-bits command word is made of:
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* bit[15]: direction bit, read is 1, write is 0
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* bit[14:8]: command code. Identifies the command being executed, the amount of
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data words and their meaning
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* bit[7:1]: I3C address of the device this command is addressed to
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* bit[0]: reserved/parity-bit
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Backward compatibility with I2C devices
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=======================================
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The I3C protocol has been designed to be backward compatible with I2C devices.
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This backward compatibility allows one to connect a mix of I2C and I3C devices
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on the same bus, though, in order to be really efficient, I2C devices should
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be equipped with 50 ns spike filters.
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I2C devices can't be discovered like I3C ones and have to be statically
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declared. In order to let the master know what these devices are capable of
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(both in terms of bus related limitations and functionalities), the software
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has to provide some information, which is done through the LVR (Legacy I2C
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Virtual Register).
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