mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 19:46:42 +07:00
c41917df8a
Since Ingo's recent scheduler rewrite which was merged as commit
0437e109e1 sched_cacheflush is unused.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
248 lines
7.4 KiB
C
248 lines
7.4 KiB
C
#ifndef __ASM_ARM_SYSTEM_H
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#define __ASM_ARM_SYSTEM_H
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#ifdef __KERNEL__
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/*
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* This is used to ensure the compiler did actually allocate the register we
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* asked it for some inline assembly sequences. Apparently we can't trust
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* the compiler from one version to another so a bit of paranoia won't hurt.
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* This string is meant to be concatenated with the inline asm string and
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* will cause compilation to stop on mismatch. (From ARM32 - may come in handy)
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*/
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#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
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#ifndef __ASSEMBLY__
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#include <linux/linkage.h>
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struct thread_info;
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struct task_struct;
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#if 0
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/* information about the system we're running on */
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extern unsigned int system_rev;
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extern unsigned int system_serial_low;
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extern unsigned int system_serial_high;
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extern unsigned int mem_fclk_21285;
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FIXME - sort this
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/*
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* We need to turn the caches off before calling the reset vector - RiscOS
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* messes up if we don't
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*/
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#define proc_hard_reset() cpu_proc_fin()
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#endif
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struct pt_regs;
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void die(const char *msg, struct pt_regs *regs, int err)
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__attribute__((noreturn));
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void die_if_kernel(const char *str, struct pt_regs *regs, int err);
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void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
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struct pt_regs *),
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int sig, const char *name);
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#include <asm/proc-fns.h>
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#define xchg(ptr,x) \
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((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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extern asmlinkage void __backtrace(void);
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#define set_cr(x) \
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__asm__ __volatile__( \
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"mcr p15, 0, %0, c1, c0, 0 @ set CR" \
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: : "r" (x) : "cc")
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#define get_cr() \
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({ \
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unsigned int __val; \
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__asm__ __volatile__( \
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"mrc p15, 0, %0, c1, c0, 0 @ get CR" \
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: "=r" (__val) : : "cc"); \
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__val; \
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})
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extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
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extern unsigned long cr_alignment; /* defined in entry-armv.S */
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#define UDBG_UNDEFINED (1 << 0)
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#define UDBG_SYSCALL (1 << 1)
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#define UDBG_BADABORT (1 << 2)
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#define UDBG_SEGV (1 << 3)
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#define UDBG_BUS (1 << 4)
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extern unsigned int user_debug;
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#define vectors_base() (0)
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#define mb() __asm__ __volatile__ ("" : : : "memory")
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#define rmb() mb()
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#define wmb() mb()
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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#define read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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/*
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* We assume knowledge of how
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* spin_unlock_irq() and friends are implemented. This avoids
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* us needlessly decrementing and incrementing the preempt count.
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*/
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#define prepare_arch_switch(next) local_irq_enable()
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#define finish_arch_switch(prev) spin_unlock(&(rq)->lock)
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/*
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* switch_to(prev, next) should switch from task `prev' to `next'
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* `prev' will never be the same as `next'. schedule() itself
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* contains the memory barrier to tell GCC not to cache `current'.
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*/
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extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
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#define switch_to(prev,next,last) \
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do { \
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last = __switch_to(prev,task_thread_info(prev),task_thread_info(next)); \
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} while (0)
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/*
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* Save the current interrupt enable state & disable IRQs
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*/
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#define local_irq_save(x) \
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do { \
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unsigned long temp; \
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__asm__ __volatile__( \
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" mov %0, pc @ save_flags_cli\n" \
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" orr %1, %0, #0x08000000\n" \
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" and %0, %0, #0x0c000000\n" \
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" teqp %1, #0\n" \
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: "=r" (x), "=r" (temp) \
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: \
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: "memory"); \
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} while (0)
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/*
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* Enable IRQs (sti)
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*/
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#define local_irq_enable() \
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do { \
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unsigned long temp; \
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__asm__ __volatile__( \
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" mov %0, pc @ sti\n" \
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" bic %0, %0, #0x08000000\n" \
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" teqp %0, #0\n" \
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: "=r" (temp) \
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: \
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: "memory"); \
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} while(0)
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/*
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* Disable IRQs (cli)
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*/
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#define local_irq_disable() \
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do { \
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unsigned long temp; \
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__asm__ __volatile__( \
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" mov %0, pc @ cli\n" \
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" orr %0, %0, #0x08000000\n" \
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" teqp %0, #0\n" \
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: "=r" (temp) \
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: \
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: "memory"); \
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} while(0)
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/* Enable FIQs (stf) */
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#define __stf() do { \
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unsigned long temp; \
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__asm__ __volatile__( \
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" mov %0, pc @ stf\n" \
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" bic %0, %0, #0x04000000\n" \
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" teqp %0, #0\n" \
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: "=r" (temp)); \
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} while(0)
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/* Disable FIQs (clf) */
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#define __clf() do { \
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unsigned long temp; \
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__asm__ __volatile__( \
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" mov %0, pc @ clf\n" \
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" orr %0, %0, #0x04000000\n" \
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" teqp %0, #0\n" \
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: "=r" (temp)); \
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} while(0)
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/*
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* Save the current interrupt enable state.
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*/
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#define local_save_flags(x) \
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do { \
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__asm__ __volatile__( \
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" mov %0, pc @ save_flags\n" \
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" and %0, %0, #0x0c000000\n" \
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: "=r" (x)); \
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} while (0)
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/*
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* restore saved IRQ & FIQ state
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*/
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#define local_irq_restore(x) \
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do { \
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unsigned long temp; \
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__asm__ __volatile__( \
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" mov %0, pc @ restore_flags\n" \
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" bic %0, %0, #0x0c000000\n" \
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" orr %0, %0, %1\n" \
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" teqp %0, #0\n" \
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: "=&r" (temp) \
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: "r" (x) \
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: "memory"); \
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} while (0)
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#ifdef CONFIG_SMP
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#error SMP not supported
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#endif
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#define clf() __clf()
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#define stf() __stf()
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#define irqs_disabled() \
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({ \
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unsigned long flags; \
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local_save_flags(flags); \
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flags & PSR_I_BIT; \
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})
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
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{
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extern void __bad_xchg(volatile void *, int);
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switch (size) {
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case 1: return cpu_xchg_1(x, ptr);
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case 4: return cpu_xchg_4(x, ptr);
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default: __bad_xchg(ptr, size);
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}
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return 0;
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}
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#endif /* __ASSEMBLY__ */
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#define arch_align_stack(x) (x)
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#endif /* __KERNEL__ */
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#endif
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