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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b182cc4d59
Those two new SCM calls are needed from qcom-iommu driver in order to initialize secure iommu page table. Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
78 lines
3.3 KiB
C
78 lines
3.3 KiB
C
/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
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* Copyright (C) 2015 Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __QCOM_SCM_H
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#define __QCOM_SCM_H
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#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
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#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
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#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
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#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
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struct qcom_scm_hdcp_req {
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u32 addr;
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u32 val;
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};
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#if IS_ENABLED(CONFIG_QCOM_SCM)
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extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
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extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
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extern bool qcom_scm_is_available(void);
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extern bool qcom_scm_hdcp_available(void);
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extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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u32 *resp);
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extern bool qcom_scm_pas_supported(u32 peripheral);
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extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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size_t size);
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extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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phys_addr_t size);
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extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
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extern int qcom_scm_pas_shutdown(u32 peripheral);
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extern void qcom_scm_cpu_power_down(u32 flags);
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extern u32 qcom_scm_get_version(void);
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extern int qcom_scm_set_remote_state(u32 state, u32 id);
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extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
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extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
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extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
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#else
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static inline
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int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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{
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return -ENODEV;
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}
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static inline
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int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
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{
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return -ENODEV;
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}
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static inline bool qcom_scm_is_available(void) { return false; }
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static inline bool qcom_scm_hdcp_available(void) { return false; }
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static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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u32 *resp) { return -ENODEV; }
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static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
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static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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size_t size) { return -ENODEV; }
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static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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phys_addr_t size) { return -ENODEV; }
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static inline int
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qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
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static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
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static inline void qcom_scm_cpu_power_down(u32 flags) {}
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static inline u32 qcom_scm_get_version(void) { return 0; }
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static inline u32
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qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
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static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
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static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
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static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
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#endif
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#endif
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